Metal interconnections are expected to become the limiting factor for the performance of electronic systems as transistors continue to shrink in size. Replacing them by optical interconnections, at different levels ranging from rack-to-rack down to chip-to-chip and intra-chip interconnections, could provide the low power dissipation, low latencies and high bandwidths that are needed. The implementation of optical interconnections relies on the development of micro-optical devices that are integrated with the microelectronics on chips. Recent demonstrations of silicon low-loss waveguides, light emitters, amplifiers and lasers approach this goal, but a small silicon electro-optic modulator with a size small enough for chip-scale integration has not yet been demonstrated. Here we experimentally demonstrate a high-speed electro-optical modulator in compact silicon structures. The modulator is based on a resonant light-confining structure that enhances the sensitivity of light to small changes in refractive index of the silicon and also enables high-speed operation. The modulator is 12 micrometres in diameter, three orders of magnitude smaller than previously demonstrated. Electro-optic modulators are one of the most critical components in optoelectronic integration, and decreasing their size may enable novel chip architectures.

Micrometre-scale silicon electro-optic modulator

We have developed a new method to analyze the forward ac behavior of a semiconductor diode that uses a series mode. This method can accurately measure the dependence of series resistance, junction capacitance, junction voltage, ideality factor, and interfacial layer on forward bias voltages. Giant negative capacitance (NC) of the junction and the interfacial layer with nonlinear resistance and capacitance are confirmed in GaN Schottky diodes.

Accurate electrical characterization of forward AC behavior of real semiconductor diode: giant negative capacitance and nonlinear interfacial layer

A principal feature of the present invention is to clean a surface of a semiconductor substrate without providing a damaged layer to the surface thereof. A native oxide film formed on the surface of a silicon substrate is etched by plasma employing a gas containing fluorine. The surface of the semiconductor substrate is again subjected to plasma etching by employing a gas containing fluorine in order to remove a surface damaged layer and a fluorocarbon layer formed in the above step of plasma etching. The semiconductor substrate surface is irradiated with ultraviolet rays under a low pressure in order to dissociate and remove fluorine atoms chemically adsorbed to the semiconductor substrate surface upon the latter plasma etching.

Method of treating semiconductor substrate surface and method of manufacturing semiconductor device including such treating method

A test circuit is described for measuring the specific contact resistivity r c of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance r s of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned common controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept ON by means of an applied above-threshold control voltage, while a current source forces current through one of the transistors. The resulting voltage, developed across the common controlled electrode and the controlled electrode of the other transistor is a measure of the specific contact resistivity thereat.

Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits

The improvement of Al-to-Si contact performance to a low contact resistance of 0.4 mu Omega -cm/sup 2/ and a Schottky junction having an n factor of 1.02 without any thermal treatment has been achieved by a native-oxide-free processing technique. The technique consists of N/sub 2/-gas-sealed wet cleaning using pure water with low dissolved oxygen (20 p.p.b.), wafer transport and loading in an N/sub 2/ environment, and Al deposition by low-energy ion bombardment. >

Improvement of aluminum-Si contact performance in native-oxide-free processing

Prealloy and postalloy contact resistances at [(Al–Si)/bulk (100)Si] interfaces have been measured for a range of Al–Si alloy compositions (0–2 at.% Si), alloying temperatures (325–550 °C), and contact sizes (3–5 μm). Contact doping for n+/p junctions was by diffusion from a POCl3 source; for p+/n junctions, by diffusion from a BN source. Al–Si deposition was by S–Gun■ magnetron sputtering. Statistical distributions of prealloy contact resistance to n+ Si were found to provide highly sensitive monitors of contact cut and deposition‐system cleanliness.. Minimum postalloy contact resistance values were independent of Al–Si alloy composition, and silicon pitting in the contact cut was not required to achieve good Ohmic contact. The maintenance of consistent, low‐resistance Ohmic contacts throughout postalloy processing was found to depend on the silicon concentration in the aluminum being high enough to keep the aluminum supersaturated during all postdeposition temperature cycling.

Contact resistance: Al and Al–Si to diffused N+ and P+ silicon

Les nettoyages in situ a l'aide de plasmas reagissant de CF 4 et de plasmas de pulverisation par Ar sont compares au nettoyage par plongee dans HF dilue des contacts Al 1% Si/Si n + de dimensions (1 μm) 2 a (3 μm) 2 . Le traitement par CF 4 sous pression ≥100 mtorr donne des resistances de contact moyennes apres alliage deux fois plus faibles qu'apres lavage dans HF et des valeurs plus coherentes. La pulverisation par Ar donne une resistance de contact elevee (>300 Ω) quand Al est present dans la decharge. Une paillette de Mo pour eviter que Al ne se redepose sur les surfaces de contact pendant le nettoyage donne des resistances de contact excellentes avant alliage. Cependant, ces contacts se degradent au cours de l'alliage a 425°C et pendant les cycles thermiques vers 300°C

Comparative Investigation of CF 4 ‐ Plasma , Ar‐Plasma, and Dilute ‐ HF ‐ Dip Cleaning Methods for (Al‐Si)/n+Si Contacts

Methods for detecting increases in oxygen concentration in aluminum‐based integrated‐circuit (IC) metallizations through increases in monitor‐film resistivity have been developed. Since the resistivity of the IC film is itself not sensitive to small changes in oxygen concentration, monitor configurations were designed such that the ratio of oxygen‐species to aluminum‐atom flux on the monitor substrate was many times higher than that on the IC substrates. This resulted in a higher oxygen concentration in the monitor films and a stronger dependence of film resistivity on system oxygen concentration. Monitors were tested in an E‐beam evaporator and in an S‐Gun magnetron sputtering system during the deposition of aluminum films in a residual‐gas environment, and during the deposition of Al–O films deposited with oxygen inputs to the system. Enhancement of the oxygen to aluminum flux ratio was accomplished by shuttering or canting the monitor substrate to decrease the aluminum flux, or by placing it close to t...

Oxygen monitors for aluminum and Al–O thin films

Chronic problems have been experienced in integrated circuit fabrication lines in the formation of Ohmic contacts between Al–Si interconnect metallization and device (bulk or epi) silicon. One of the reasons for such problems has been the absence of a simple and reliable method for predicting, immediately after metal deposition, whether or not the contact resistances in the finished circuits will be satisfactory. This paper describes and demonstrates such a method for (Al–1% Si)/(phosphorus‐implanted) n+ Si contacts.

R. S. Irven

Papers

Contact resistance: Al and Al–Si to diffused N+ and P+ silicon

Comparative Investigation of CF 4 ‐ Plasma , Ar‐Plasma, and Dilute ‐ HF ‐ Dip Cleaning Methods for (Al‐Si)/n+Si Contacts

Oxygen monitors for aluminum and Al–O thin films

Contact resistance monitor for silicon integrated circuits