IEEE International Solid-State Circuits Conference

Gate Diffusion Input technique based full swing and scalable 1-bit hybrid Full Adder for high performance applications

This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V DD and V T to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V DD for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-μm test chip is used to compare normal sizing and sizing to minimize operational V DD and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.

Modeling and sizing for minimum energy operation in subthreshold circuits

A high-speed and scalable XOR-XNOR-based hybrid full adder design

Digital signal processing (DSP) systems are becoming popular with the emergence of artificial intelligence and machine learning based applications. Residue number system is one of most sought representation for implementing the high speed DSP systems. This paper presents an efficient implementation of memory less distributed arithmetic (MLDA) architecture in finite impulse response filter with residual number system. The input data and filter coefficients of MLDA are in residue number form and the output data from MLDA is converted into binary form using Chinese remainder theorem. In addition, compressor adders are used to reduce the area. For real time validation, the proposed design has been simulated and synthesized in application specific integrated circuit platform using synopsis design compiler with CMOS 90 nm technology. The results show that the proposed design has very high computation speed with total delay of only 20 ns and occupies 20% less area in comparison with the existing designs.

ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems

In recent years, ultra-low-voltage (ULV) operation is gaining more importance for achieving minimum energy consumption. Full adder is the basic computational arithmetic block in many of the computing and signal/image processing applications. Here, a new hybrid 1-bit full adder circuit which employs both Gate Diffusion Input (GDI) logic and multi-threshold voltage (MVT) transistor logic is reported. The main objective of the proposed MVT-GDI-based hybrid full adder design is to provide minimum energy consumption with less area. The proposed hybrid design is simulated using standard 45 nm CMOS process technology at an ULV of 0.2 V. The post-layout simulation results have shown that the proposed design achieved significant improvements in comparison with the other reported designs by achieving >57%, 92% savings in the Energy and EDP, respectively, with only 14 transistors. Monte–Carlo simulations have also been performed and is found that the proposed design methodology yields full functionality and robustness against local and global process variations. Normalised energy metrics to 32 and 22 nm technologies shows that the proposed design achieves >57% energy savings in prior to the recent works.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2018.5559

Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems

The Internet of Things is an emerging application area which is going to become one of the leading electronic hubs in the semiconductor industry. The IoT systems require battery-enabled energy-efficient memory circuits to operate at ultra-low voltage (ULV). In this paper, a novel Schmitt trigger-based, single-ended 7-Transistor (7T) Static Random Access Memory (SRAM) cell which uses dynamic body bias technique for IoT applications is presented. The proposed 7T SRAM cell is designed using standard 45nm Complementary Metal Oxide Semiconductor technology at an ULV of 0.3V. The post-layout simulation results have shown more than 22% improvements in the Read Static Noise Margin and more than 44% write, 63% read energy savings in comparison with the conventional 6T cell, 7T, single-ended 8T, and Schmitt trigger 11T cell designs. The proposed design is also found to be stable at different process corners and supply voltages. A new quality metric SNM per unit Area to Energy Ratio which evaluates the overall performance of the SRAM cell design is calculated and is found to be highest for the proposed design.

Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications

As technology advances towards the deep sub-micron regime, energy consumption of digital circuits is becoming more serious. Supply voltage (V DD ) scaling is the effective knob to achieve minimum energy consumption. This paper aims at obtaining the minimum energy optimal V DD for the design of Gate Diffusion Input (GDI) logic circuits. A 10 transistor (10T) GDI based full adder circuit is designed for analyzing the performance of GDI logic to obtain optimal V DD . Extensive simulations were performed using different supply voltages ranging from 100mV to 1V using the cadence 45nm CMOS process technology. The simulations have shown that the operation of GDI based design at optimal V DD of 0.4V, lead to energy savings of more than 69% in comparison with the strong inversion counterparts. The expressions for energy using GDI logic have also been presented.

Analysis of GDI logic for minimum energy optimal supply voltage

This paper proposes a modified form of the design for low dynamic power adder using a reset network in the CMOS dynamic logic family. The results show that the dynamic power reduces as compared to lower dynamic power logic and the domino logic. In this modified form of the low dynamic power adder, the logic outputs are reset to low during the pre-discharge phase which is the high input to the clock. The logic evaluation takes place when the clock input is low. The modified logic is better than domino logic since it does not require an inverter for cascading the gates. In Pre-discharging, resetting the output low prevents the problems of charge sharing and charge leakage associated with the other dynamic logic families and also it avoids the static power dissipation which exists in the low power dynamic logic. Also resetting the output low avoids the problem of high transition time from high level to low level which exists in circuits employing PMOS logic. The proposed circuit is a mix of PMOS logic and a dynamic logic. The proposed logic cell can be cascaded in a domino like fashion without the need of an inverter.

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Modified Low Power Dynamic Adder for High Performance

Advanced Encryption Standard (AES) is an effective cryptography algorithm for providing the better data communication since it guaranties high security. The Galois/Counter Mode (AES-GCM) has been integrated in various security constrained applications because it provides both authentication and confidentiality. AES algorithm helps to provide data confidentiality while authentication is provided by a universal GHASH function. Since most of existing GCM architectures concentrated on power and area reduction but an compact and efficient hardware architecture should also be considered. In this paper, high-performance architecture for GCM is proposed and its implementation is described. In order to achieve higher operating frequency and throughput, pipelined S-boxes are used in AES algorithm. For a GCM realization of AES, a high-speed, high-throughput, parallel architecture is proposed. Experimental results proves that the performance of the proposed work is around 17% higher than the existing architecture with 3 Gb/s throughput using TSMC 45-nm CMOS technology.

R. Sakthivel

Papers

Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems

Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications

Analysis of GDI logic for minimum energy optimal supply voltage

Modified Low Power Dynamic Adder for High Performance

High Performance GCM Architecture for the Security of High Speed Network