A MOS comparator which includes a capacitor connected in an electrical path between two amplification stages. The comparator also includes a voltage source, and a switch is provided between the voltage source and the input of the second stage. A variability of electrical parameter of the voltage source can be matched with a parameter of the amplification stage. The comparator can also include another switch between another voltage source and a third stage, with the two voltage sources providing different voltages. A comparator gain stage includes circuitry for deriving a differential current from the two voltages. Circuitry is also provided for loading the differential current to derive an amplified difference voltage. Further circuitry is provided for bypassing the loading circuity to reduce a quiescent voltage drop associated with the loading circuitry.

Low-voltage CMOS comparator

A charge redistribution analog-to-digital converter. This converter includes an offset correcting circuit operatively connected in parallel with a capacitor array and responsive to a sampling input of the analog-to-digital converter, and a gain correcting circuit operatively connected in parallel with a sampling capacitor and responsive to the sampling input of the analog-to-digital converter. In another general aspect, an analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, that includes adjusting an input offset of an input of the analog-to-digital converter and adjusting a gain offset of the analog-to-digital converter. The steps of adjusting are then repeated until a predetermined level of error is achieved for the analog-to-digital converter.

Charge redistribution analog-to-digital converter with system calibration

Performing a coarse conversion of an analog signal to a coarse digital representation using a first analog-to-digital converter, transferring the coarse representation to a second converter, and performing a fine analog-to-digital conversion of the signal using the coarse representation as a starting value for a fine digital representation. The fine conversion can include a redundant portion that can be used to correct a mismatch between the coarse and fine conversions, and this correction can operate according to a combinatorial transfer function. The fine conversion may include switching from a coarse reference to a fine reference after transferring the coarse representation. The fine conversion can also include comparing an amount of charge in a sampling capacitor after performing the coarse conversion. Also disclosed is converting an analog signal to a digital representation having a first resolution level, adjusting a bandwidth of the converter circuit, and then continuing to convert the analog signal to a second, higher resolution level. The adjusting can include adjusting a bandwidth of a comparison circuit. Further disclosed is evaluating the amount of charge stored in a second sampling capacitor while tracking an analog signal with the first sampling capacitor. The amount of charge stored in the first capacitor is evaluated while tracking the signal with the second capacitor. Evaluating the amount of charge in the first capacitor can include comparing performed in part by a first comparator input stage, evaluating the amount of charge in the second capacitor can include comparing performed in part by a second comparator input stage. Analog-to-digital conversion circuitry can be multiplexed between the sampling capacitors.

Analog-to-digital conversion with multiple charge balance conversions

A family of C-2C ladder-based D/A (digital-to-analog) converters is presented. The best of these uses only 43 unit capacitors to implement a 13-b converter for use in PCM (pulse-code modulation) codecs. The practical feasibility of these networks is confirmed by actual on-chip implementation.

C-2C ladder-based D/A converters for PCM codecs

A compact analog-to-digital converter (ADC) system suitable for high-resolution gamma-ray detectors has been developed around the Burr Brown PCM78P 16-b audio ADC. An associated application-specific integrated circuit (ASIC), handling four ADCs, provides sliding scale circuitry, lower threshold adjustment, channel number identification, and zero suppression. The conversion time is 4.5 mu s, and the differential nonlinearity, for 13-b resolution, is less than +or-0.8%. >

Analog to digital converter

A charge redistribution codec fabricated by NMOS technology is presented which uses only one capacitor array, thereby resulting in improved accuracy, speed, and chip area utilization. The realization of this scheme requires precision voltage references which are described. A description of a codec complete with logic to interface a full duplex PCM link is included. The chip has provision for asynchronous transmit/receive, direct and microcomputer control and internal power down. The introduction of an improved method for offset correction eliminates the need for off-chip autozero circuitry.

Charge redistribution codec

A new charge redistribution codec is presented which uses a single capacitor array, thereby resulting in improved accuracy, speed and chip area use. The codec realization requires precision reference voltages and offset correction, which are also described in this paper.

R.W. Zahora

Papers

Charge redistribution codec

Charge Redistribution Codec