A video teleconferencing system uses digital transcoding to obtain algorithm transcoding, transmission rate matching, and spatial mixing. The video teleconferencing system comprises a multipoint control unit (MCU) for allowing multiple audiovisual terminals, which send and receive compressed digital data signals, to communicate with each other in a conference. The MCU has a video processing unit (VPU) that performs algorithm transcoding, rate matching, and spatial mixing among the terminals within a conference. The VPU includes a time division multiplex pixel bus and a plurality of processors. Each processor is assignable to an audiovisual terminal in the conference and is coupled to the pixel bus. In a receive mode, each processor receives and decodes compressed video signals from its assigned terminal and puts the decoded signal onto the pixel bus. In a transmit mode, each processor receives from the pixel bus uncompressed video signals from any terminal in the conference. The uncompressed video signals are processed and encoded for transmission to the respective assigned terminal. Video encoding time due to motion displacement search is reduced by passing displacement information from the compressed video signals to the encoder to be used directly or as a seed for further refinements of the motion displacement field.

Video teleconferencing system with digital transcoding

A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

Method and apparatus for memory array compressed data testing

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Apparatuses and methods for performing compare operations using sensing circuitry

Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

Division operations for memory

An integrated semiconductor circuit includes word lines and bit lines. A memory region has at least one memory cell field with memory cells addressable through the word lines and the bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.

Integrated semiconductor circuit

An integrated semiconductor memory of the DRAM type includes word lines and bit line pairs. Memory cells in a matrix are connected to the word lines and the bit lines. One evaluator circuit per bit line pair is connected to the bit lines. Each of the bit line pairs is divided into one bit line and one reference bit line during operation. A control line is provided. At least one coupling capacitor is provided for each of the bit lines and each of the reference bit lines having a first lead connected to the bit line pair and a second lead connected to the control line. A method for testing an integrated semiconductor memory of the DRAM type includes reading data stored in memory cells out of the memory cells, precharging bit line pairs to a precharge level before reading out, and feeding an additional potential to each bit line pair after precharging.

Integrated semiconductor memory of the dram type and method for testing the same

A band gap reference circuit configuration includes first and second bipolar transistors having base-to-emitter voltages. An emitter resistor is connected to the first bipolar transistor. An operational amplifier is connected to the bipolar transistors for processing a difference generated between the base-to-emitter voltages of the first and second bipolar transistors to generate a largely temperature-independent reference voltage. The bipolar transistors are parasitic transistors, and the operational amplifier is constructed in MOS technology.

Cmos band gap reference circuit

A circuit configuration and method for testing storage cells of an integrated semiconductor memory precharges a pair of external bit lines to mutually complementary logic levels. All of the storage cells of a word line are always read-out in parallel. In a "no fault" situation the pair of external bit lines retains its precharge level, whereas in the case of a fault, the level of the external bit line which is precharged to logical 1 falls. This is recognized by a discriminator circuit and analyzed.

Circuit configuration and a method of testing storage cells

In the method according to the invention, the same data are written to corresponding memory cells (SZ) of two blocks (B1, B2) of a semiconductor memory. All the memory cells (SZ) of two corresponding word lines (WL) of the blocks (B1, B2) are read out simultaneously. The data are amplified and compared with one another. The result is fed to an error signal (F). A circuit which makes it possible to carry out this method is presented. The invention can also be used in the case of video RAMs.

Rainer Dipl.-Phys. Kraus

Papers

Integrated semiconductor circuit

Integrated semiconductor memory of the dram type and method for testing the same

Cmos band gap reference circuit

Circuit configuration and a method of testing storage cells

Method and circuit arrangement for testing a semiconductor memory