International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

We propose a Heterojunction Vertical Tunneling FET and show using self-consistent ballistic quantum transport simulations that it can provide very steep subthreshold swings and high ON current, thereby improving the scalability of Tunnel FETs for high performance. The turn-on in pocket region of the device is dictated by modulation of heterojunction barrier height. The steepness of turn-on is increased because of simultaneous onset of tunneling in the pocket and the region underneath and also due to contribution to current by vertical tunneling in the pocket. These factors can be engineered by tuning heterojunction band offsets.

Heterojunction Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High ON Current

A two dimensional dual-k spacer overlapped double gate hetero-structure PNPN tunnel field effect transistor (DS-DG-PNPN-TFET) structure is proposed and its electrical parameters are optimized using the 2D-TCAD device simulator Optimization is performed by varying the device dimension and doping concentration to get the better result of ON current (I ON ), I ON /I OFF ratio and sub-threshold swing (SS) The p-type Germanium source, optimized doping concentration 1x1020 cm-3 with a 2 nm SiGe pocket counter doped with 5×1018 cm-3 concentrations showed better performance in the overlapped double gate structure in terms of ON current (17 mA), ON-OFF ratio (1011) and SS (31 mV/decade) when compared to a conventional double gate tunnel field effect transistor (DG-TFET) with high-k gate dielectric (HfO 2 ) AC analysis also showed improved result in terms of total gate capacitance (C gg ), gate-drain capacitance (C gd ) and cut-off frequency (f T ) etc

Optimization of Electrical Parameters in Dual Dielectric Spacer Overlapped DG Tunnel FET

In this article, a comprehensive comparison of Si-SiGe hetero-junction tunnel field effect transistor (TFET) and conventional TFET is presented The Silicon-Germanium (SiGe) pocket utilized in the proposed TFET structure reduces the tunneling distance to provide enhanced ON current as compared to the conventional one Moreover, the proposed heterojunction TFET offers super-steeper sub-threshold swing (SS) of 14 mV/dec The temperature dependence characteristics and its impact on interface traps for both the structures are explored and examined Results expose that TFET shows less temperature dependence in the ON state due to band to band tunneling mechanism of current conduction While, in the OFF state the temperature dependency is increased It is found that the TFET has less effect of interface traps on ON current degradation than leakage current It is also found that the proposed hetero-junction TFET shows better immunity against trap effect even under temperature variation as compared to the conventional TFET This confirms the superiority and reliability of the proposed hetero-junction TFET for recent semiconductor industries

Raju Pandey

Papers

Optimization of Electrical Parameters in Dual Dielectric Spacer Overlapped DG Tunnel FET

Impact of Temperature and Trap Charges on Heterojunction Tunnel FET