Proceedings ArticleDOI
Optimization of Electrical Parameters in Dual Dielectric Spacer Overlapped DG Tunnel FET
TLDR
In this paper, a two dimensional dual-k spacer overlapped double gate hetero-structure PNPN tunnel field effect transistor (DS-DG-PNPN-TFET) structure is proposed and its electrical parameters are optimized using the 2D-TCAD device simulator.Abstract:
A two dimensional dual-k spacer overlapped double gate hetero-structure PNPN tunnel field effect transistor (DS-DG-PNPN-TFET) structure is proposed and its electrical parameters are optimized using the 2D-TCAD device simulator Optimization is performed by varying the device dimension and doping concentration to get the better result of ON current (I ON ), I ON /I OFF ratio and sub-threshold swing (SS) The p-type Germanium source, optimized doping concentration 1x1020 cm-3 with a 2 nm SiGe pocket counter doped with 5×1018 cm-3 concentrations showed better performance in the overlapped double gate structure in terms of ON current (17 mA), ON-OFF ratio (1011) and SS (31 mV/decade) when compared to a conventional double gate tunnel field effect transistor (DG-TFET) with high-k gate dielectric (HfO 2 ) AC analysis also showed improved result in terms of total gate capacitance (C gg ), gate-drain capacitance (C gd ) and cut-off frequency (f T ) etcread more
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Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering
TL;DR: It is shown here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to Tunnel FET scaling.