In VLSI, for performing multiplication, we use a*b. We use the booth multiplication mechanism rather than the standard conventional method to improve the speed since it generally requires lower power, area and reduces delay. Some bits overlap with each other during the multiplication process in the convectional multiplication method (whereas booth multipliers consist of shifting process), making the system more complex and decreasing output efficiency. To overcome this, SPST is implemented such that unwanted transactions are neglected and also eliminate the overlapping bits. This affects the carry changes and data generation parts and even reduces the unwanted power flow in adders. It uses Radix 4 multiplier, which requires addition processors. In the previous multipliers usage of Ripple carry adder, Carry save adder, carry ahead adder, which are the basic types of serial adders where they utilize serial adding mechanism where the data is processed bit by bit that make the system more complicated. To reduce these problems, we are using parallel prefix adders that work in a higher speed manner, which uses carry propagation and carry generation internally to perform additional operations and improve speed. So, this project is implemented in VLSI prototype with respect to Xilinx ISE software and Verilog programming language. 

Implementation of Spurious Power Suppression based Radix-4 Booth Multiplier using Parallel Prefix Adders

Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application

Designing of an 8 × 8 Multiplier with New Inexact 4:2 Compressors for Image Processing Applications

With the popularization of the Internet and the rapid development of new technologies such as artificial intelligence, cloud computing, and the Internet of Things(ITS), the explosive growth of data traffic puts forward higher requirements for transmission performance. In order to meet the ever-increasing demand for capacity and cope with the ensuing crisis, the application of digital signal processing technology in the communications field is imperative. With the development of high-speed integrated circuits and digital signal processing algorithms and other technologies, high-speed digital signal processing has become increasingly mature, and ITS has become one of the global research hotspots. The country is also strategically advancing the research on ITS. This article mainly uses the experimental analysis method to explore whether the application of digital signal processing technology can provide a new idea for the development of the communication field in the context of ITS. In the experiment, this article analyzes the OPA multiplexing mode demodulation energy and crosstalk energy, and analyzes the changes of the bit error rate under different communication rates and different communication distances. According to the experimental results, OPA multiplexing transmission has a certain degree of stability. The combination of OPA mode multiplexing technology and traditional systems can provide more possibilities for building communication networks with higher capacity systems in the future. As the communication rate and communication distance increase, the bit error rate will increase accordingly. Therefore, this article studies the application of digital signal processing technology in the communication field under the background of ITS, which has huge application potential and research value. 

Digital Signal Processing Technology in the Communication Field under the Background of the Internet of Things

With the popularization of the Internet and the rapid development of new technologies such as artificial intelligence, cloud computing, and the Internet of Things(ITS), the explosive growth of data traffic puts forward higher requirements for transmission performance. In order to meet the ever-increasing demand for capacity and cope with the ensuing crisis, the application of digital signal processing technology in the communications field is imperative. With the development of high-speed integrated circuits and digital signal processing algorithms and other technologies, high-speed digital signal processing has become increasingly mature, and ITS has become one of the global research hotspots. The country is also strategically advancing the research on ITS. This article mainly uses the experimental analysis method to explore whether the application of digital signal processing technology can provide a new idea for the development of the communication field in the context of ITS. In the experiment, this article analyzes the OPA multiplexing mode demodulation energy and crosstalk energy, and analyzes the changes of the bit error rate under different communication rates and different communication distances. According to the experimental results, OPA multiplexing transmission has a certain degree of stability. The combination of OPA mode multiplexing technology and traditional systems can provide more possibilities for building communication networks with higher capacity systems in the future. As the communication rate and communication distance increase, the bit error rate will increase accordingly. Therefore, this article studies the application of digital signal processing technology in the communication field under the background of ITS, which has huge application potential and research value.

Approximate computing is a striking approach to design area-efficient low-power datapath units for fault buoyant applications. This brief presents the design of a novel 4: 2 approximate compressor that generates no error in the carry signal. The proposed compressor is employed for partial product (PP) compression in two variants of Dadda multiplier to see its effectiveness in error-resilient image and signal processing applications. In the targeted multipliers, the approximate 4:2 compressor is used in the least n PP columns, while the exact counterpart is used in the remaining most significant columns, and hence the maximum error is precisely maintained within 2n. PP compression is performed in stages using the Wallace approach, and the final two rows of sum and carry signals are added using a ripple carry adder in the basic design. In the proposed multiplier design-2, we do not generate sum bits in the approximate part. However, the proposed error-tolerant compressor is used in appropriate columns to propagate carry to the least significant column in the exact part. Performance evaluations using Cadence Encounter with 90 nm application specific integrated circuit technology revealed that the proposed-full width (P-FW) and the proposed-truncated (P-Trun) approximate multipliers demonstrate 22.7% and 32.4% power-delay product reduction compared to the standard multiplier. Implementations of the proposed multipliers in signal and image processing applications revealed superior performance in terms of accuracy compared to prior similar approximate designs.

Ramya Ramasamy

Papers

Area–Energy–Error Optimized Faithful Multiplier for Digital Signal Processing