The bipolar transistor and FET are compared, considering both today's most advanced implementations and "ultimate" scaled-down devices. The differences between the devices are quantified in terms of transconductance and intrinsic speed. Old limits are re-examined and ways of extending the devices toward their ultimate in performance are proposed. While the major emphasis is on silicon, a comparison is made with the GaAs MESFET. Other semiconductor devices are discussed in the context of "bipolar-like" and "FET-like" devices, and the HEMT is considered a very promising candidate for high-speed logic. While Josephson junction logic is not discussed at length, it is a continual point of reference. In addition to comparing devices, the on-chip wiring environment is discussed, especially concerning its impact on power-delay products.

A comparison of semiconductor devices for high-speed logic

A method for manufacturing a semiconductor device which comprises the steps of forming a first groove in that portion of a semiconductor substrate where an isolation is to be formed; selectively forming a second groove narrower than the first groove in that surface region of the semiconductor substrate which is surrounded by said first groove; depositing a masking material over the whole surface of the semiconductor substrate with a thickness less than half the width of the first groove and greater than half the width of the second groove; aniotropically etching the deposited masking material to eliminate substantially its thickness, thus leaving the masking material on the side walls of the first groove and entirely in the second groove; introducing an impurity into the bottom of the first groove to form an impurity region; filling the first groove with an isolating material; and forming a semiconductor element in that section of the semiconductor substrate which is surrounded by an isolation consisting of the impurity region and the isolating material layer in the first groove The semiconductor-manufacturing method of the invention forms an element isolation consisting of an isolating material filling the first groove and an impurity region, and also an interelement isolation region consisting of an isolating material filling the second groove which is narrower than the first groove, both isolations being formed with high precision

Method for manufacturing semiconductor device

Many integrated circuits include a type of transistor known as a metal-oxide-semiconductor, field-effect transistor, or “mosfet,” which has an insulated gate member that controls its operation. Early mosfets had aluminum gates. But because the aluminum made the mosfets unreliable and difficult to manufacture, aluminum was abandoned in favor of polysilicon. Unfortunately, polysilicon has ten-times more electrical resistance than aluminum, which not only wastes power but also slows operation of the integrated circuits. Several efforts have been made to use materials less-resistive than polysilicon, but these have failed to yield a practical solution, since some of the materials have high electrical resistance and prevent low-voltage operation. Accordingly, one embodiment of the invention provides a gate structure that includes a doped polysilicon layer to facilitate low-voltage operation, a diffusion barrier to improve reliability, and a low-resistance aluminum, gold, or silver member to reduce gate resistance. Moreover, to overcome previous manufacturing difficulties, the inventors employ a metal-substitution fabrication technique, which entails formation of a polysilicon gate, and then substitution of metal for the polysilicon.

Highly conductive composite polysilicon gate for CMOS integrated circuits

An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

Isolation for high density integrated circuits

Improved resistance to electrical instability of opto-isolators subjected to large stand-off voltages is obtained by coating the semiconductor light sensing element with a high resistivity layer of amorphous silicon while leaving most of the surface PN junction perimeter and nearby regions free of metal. The amorphous silicon prevents mobile ions in the encapsulation, which are driven to the detector surface by the stand-off voltage, from inverting or modulating the conductivity of the detector surface and causing instability. The amorphous silicon also makes it possible to leave most of the light sensitive PN junctions and nearby regions free of metal, thereby simplifying design of complex IC detector chips and increasing sensitivity.

Complex opto-isolator with improved stand-off voltage stability

A bipolar transistor device is disclosed having a structure wherein a layer of insulating material extends over and covers the structure substrate up to the region of the extrinsic base around the emitter. A very small area conductive base contact is provided to the extrinsic base, and a protective wall of insulating material is located on the sidewall of the base contact to isolate it from the emitter contact. This structure is made possible by a fabrication process incorporating a double-self-alignment technique wherein the base is self-aligned to a window in the insulating material and the emitter is self-aligned to the base.

Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area

An inverted polycide extrinsic base contact serves as a diffusion source, yet still has low resistivity and is readily etchable down to silicon by techniques useful in manufacturing integrated circuits. The extrinsic base contact layer is made up of a metal silicide (e.g. WSi2) with an overlying doped polysilicon layer with coextensive apertures through doped polysilicon and metal silicide layers defining the emitter and intrinsic base region. The extrinsic base region is formed by diffusing boron impurities from the p+ polysilicon layer through the silicide layer. The silicide layer is of a metal silicide such as tungsten silicide (WSi2). The polysilicon layer acts as a diffusion source, since appropriate dopants (e.g., boron) diffuse rapidly through the metal silicide. Both the top surface of the p+ polysilicon layer and the sidewall edges of the polysilicon and silicide layers are covered by an insulating layer (e.g. SiO2) which also separates the emitter contact from the base contact layers.

Self-aligned bipolar transistor with inverted polycide base contact

An integrated circuit containing a refractory metallic silicide beneath a field isolation region and in electrical contact with electrical conductive regions of active impurity dopants in a semiconductive substrate; and process for the fabrication thereof.

Integrated circuit having a sublayer electrical contact and fabrication thereof

A vertical bipolar transistor structure has an extrinsic base region (4) covered by a metal silicide (eg WSi 2 ) layer (6) and a doped (eg with boron) polysilicon layer (7). The metal silicide and polysilicon layers (6, 7) have an opening therein with which the emitter (3) and intrinsic base region (2) of the transistor are aligned. The vertical bipolar transistor structure can be produced by a method including delimiting a transistor area in a semiconductor substrate, depositing in succession over the the transistor area a silicide layer (6), a doped polysilicon layer (7) and a silicon dioxide layer (8), forming an aperture through the silicon dioxide, the doped polysilicon and the silicide layers, forming an insulating layer (8A) over the transistor area and driving in dopant from the polysilicon layer to form an extrinsic base region (4), removing the insulating layer from the base of the aperture but not from the sidewall of the aperture and forming an intrinsic base region and an emitter aligned with the aperture and the extrinsic base region.

Transistor having emitter self-aligned with an extrinsic base contact and method of making it

IN THIS PAPER we report the characteristics of 1.25pm ECL circuits with maximum speed of 114ps ata power dissipation of 4.9mW. Such performance is achieved through the combination of properly designed bipolar devices and an advanced bpolar technology featuring self-ali ed polysilicon-base contact and deep-groove device isolation?. The 1.25pm minimum feature size was defined using electron-beam lithography.

Randall D. Isaac

Papers

Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area

Self-aligned bipolar transistor with inverted polycide base contact

Integrated circuit having a sublayer electrical contact and fabrication thereof

Transistor having emitter self-aligned with an extrinsic base contact and method of making it

1.25µm deep-groove-isolated self-aligned ECL circuits

Randall D. Isaac

Papers

Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area

Self-aligned bipolar transistor with inverted polycide base contact

Integrated circuit having a sublayer electrical contact and fabrication thereof

Transistor having emitter self-aligned with an extrinsic base contact and method of making it

1.25&#181;m deep-groove-isolated self-aligned ECL circuits

1.25µm deep-groove-isolated self-aligned ECL circuits