A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

Adaptive power control

Methods and apparatus for providing wireless communications using subframe partitioning are disclosed. Two or more base stations may be allocated subframes in a radio frame. All or part of the subframe allocation may be provided to the associated user equipment (UEs), which may use it to determine signal metrics during assigned subframes for an associated base station.

Methods and apparatus for subframe interlacing in heterogeneous networks

A method and system (130) for controlling sensed CPU dynamic operating characteristics, such as CPU temperature, temperature change and power consumption, including the steps of and circuitry for sensing at least one dynamic CPU operating characteristic (140) while the CPU operates at a first clock rate (134). The system (130) determines that a setpoint interrupt condition exists (140), such as a temperature threshold, by virtue of the at least one sensed CPU dynamic operating characteristic establishing a predetermined relationship relative to a predetermined setpoint (140) that associates with the at least one dynamic operating characteristic. In the event that the setpoint interrupt condition exists, the circuitry and instructions control (144) the clock rate relative to the first clock rate. In the event that the setpoint interrupt condition does not exist, the circuitry and instructions repeat the above steps of determining the interrupt condition and controlling the clock rate. The method and system (130) also determine whether the CPU is in a compute-bound state (142). This operation in conjunction with a real-time power conservation apparatus and method (20) is a particularly attractive feature of the present invention.

Method and apparatus for real-time CPU thermal management and power conservation by adjusting CPU clock frequency in accordance with CPU activity

Methods and apparatus for partitioning resources for enhanced inter-cell interference coordination (eICIC) are provided. Certain aspects involve broadcasting a message indicating time-domain resource partitioning information (RPI), where a user equipment (UE) may be operating in idle mode. With the RPI, the UE may be able to identify protected resources with reduced/eliminated interference from neighboring cells. The RPI in this broadcasted message may be encoded as a bitmap as an alternative or in addition to enumeration of the U/N/X subframes. Other aspects entail transmitting a dedicated or unicast message indicating the time-domain RPI, where a UE may be operating in connected mode. With the RPI, the UE may be able to determine channel state information (CSI), make radio resource management (RRM) measurements, or perform radio link monitoring (RLM), based on one or more signals from a serving base station during the protected time-domain resources.

Resource Partitioning Information for Enhanced Interference Coordination

A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The programmable array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the programmable blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.

Programmable microcontroller architecture(mixed analog/digital)

A microprocessor includes a clock control system for varying its internal processor clock frequency. The clock control system includes a delay chain composed of delay elements. A set of tap points are distributed at the outputs of selected delay elements. Each tap point is coupled to a respective input line of a latch unit. During operation, an external clock generator provides a clock signal to an input of the delay chain. As a particular rising or falling edge of the clock signal propagates through the delay chain, corresponding signal transitions sequentially appear at the tap points. The latch unit stores the signals in response to a subsequent rising or falling edge of the external clock signal. Thus, an output of the latch unit is indicative of a delay associated with the microprocessor. A decoding circuit may be provided to decode the output of the latch unit and to provide an input to a clock switching circuit which controls the frequency of an internal clock signal. If a high propagation delay exists, the frequency of the internal clock is decreased. If a low propagation delay exists, the frequency is increased.

Clock control system for microprocessors including a delay sensing circuit

A random number generator generates high quality random numbers by sampling the output of a voltage controlled oscillator (VCO) at a frequency much lower than the frequency of the oscillator output. The output frequency of the oscillator is changed significantly during each sampling interval to help ensure the phase relationship of the VCO output and the sampling frequency is unpredictable. That may be accomplished by logically combing the sampling clock and an output from a linear feedback shift register in an exclusive OR gate and supplying that output as the most significant bit used to generate the voltage to control the oscillator. Additional outputs from the linear feedback shift register are also used to generate the control input to the VCO. A distilling circuit such as a CRC circuit or a linear feedback shift register shifts in successive output samples and generates a number therefrom to further increase the randomness of the generated random number.

Method and apparatus for generating random numbers

An output buffer having a controlled output slew rate comprises a first predriver circuit having a first RC circuit and a first output node and a second predriver circuit having a second RC circuit and a second output node. A buffer input node is coupled to the first and second predriver circuits. The output buffer further includes an output circuit having first and second input nodes and a third output node, where the first and second input nodes are coupled, respectively, to the first and second output nodes. The time constants of the RC circuits control a signal slew rate at the third output node of the output circuit, and the value of R may be selected to provide a predetermined, controlled slew rate range at the third output node. A selection circuit aids in the selection of an appropriate value for R.

Output buffer with slew rate control and a selection circuit

An integrated circuit includes a dual mode output driver configured for outputting an output signal according to either a high voltage mode or a low voltage mode, and a controller for controlling the dual mode output driver at the selected mode. The dual mode output driver includes a high-voltage pull-up/pull-down driver circuit and a low-voltage pull-up/pull-down driver circuit, the low-voltage pull-down transistor in series with the high-voltage pull-down transistor that is coupled to the output node. Protection circuitry prevents the low-voltage transistors from encountering an overvoltage condition during the high voltage mode, and controls the slew rate of the output signal during the low voltage mode.

Dual-mode output driver configured for outputting a signal according to either a selected high voltage/low speed mode or a low voltage/high speed mode

A microprocessor includes a clock control system for dynamically varying the internal clock frequency of the microprocessor. The clock control system includes a delay sensing circuit coupled to a clock switching circuit. A set of tap points are distributed along a delay chain at the outputs of selected delay elements. Each tap point is coupled to a respective input line of a latch unit through a buffer unit. During operation of the processor, an external clock generator provides a clock signal to an input of the delay chain. The clock signal serially propagates through each delay element within the delay chain. As a particular rising or falling edge of the clock signal propagates through the delay chain, corresponding signal transitions sequentially appear at the tap points. The latch unit stores the signals at the delay chain tap points in response to a subsequent rising or falling edge of the external clock signal. Thus, an output of the latch unit is indicative of how far a particular edge of the clock signal propagated through the delay chain during a given period, and is thus indicative of a related delay associated with the microprocessor. A decoding circuit may be provided to decode the output of the latch unit and to provide an input to a clock switching circuit which controls the frequency of an internal clock signal to the processor core. If a high propagation delay is detected, the frequency of the internal processor clock is decreased. Likewise, if a low propagation delay is detected, the frequency of the internal clock is increased.

Randall Paul Biesterfeldt

Papers

Clock control system for microprocessors including a delay sensing circuit

Method and apparatus for generating random numbers

Output buffer with slew rate control and a selection circuit

Dual-mode output driver configured for outputting a signal according to either a selected high voltage/low speed mode or a low voltage/high speed mode

Clock control system for microprocessors