We experimentally demonstrate an ultracompact PlasMOStor, a plasmon slot waveguide field-effect modulator based on a transparent conducting oxide active region. By electrically modulating the conducting oxide material deposited into the gaps of highly confined plasmonic slot waveguides, we demonstrate field-effect dynamics giving rise to modulation with high dynamic range (2.71 dB/μm) and low waveguide loss (∼0.45 dB/μm). The large modulation strength is due to the large change in complex dielectric function when the signal wavelength approaches the surface plasmon resonance in the voltage-tuned conducting oxide accumulation layer. The results provide insight about the design of ultracompact, nanoscale modulators for future integrated nanophotonic circuits.

Nanoscale conducting oxide PlasMOStor.

To date, the preparation of free-standing 2D nanomaterials has been largely limited to the exfoliation of van der Waals solids. The lack of a robust mechanism for the bottom-up synthesis of 2D nanomaterials from non-layered materials has become an obstacle to further explore the physical properties and advanced applications of 2D nanomaterials. Here we demonstrate that surfactant monolayers can serve as soft templates guiding the nucleation and growth of 2D nanomaterials in large area beyond the limitation of van der Waals solids. One- to 2-nm-thick, single-crystalline free-standing ZnO nanosheets with sizes up to tens of micrometres are synthesized at the water-air interface. In this process, the packing density of surfactant monolayers adapts to the sub-phase metal ions and guides the epitaxial growth of nanosheets. It is thus named adaptive ionic layer epitaxy (AILE). The electronic properties of ZnO nanosheets and AILE of other materials are also investigated.

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Nanometre-thick single-crystalline nanosheets grown at the water-air interface.

Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.

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Synthesis and Characterization of Hexagonal Boron Nitride as a Gate Dielectric

Gate dielectrics directly affect the mobility, hysteresis, power consumption, and other critical device metrics in high-performance nanoelectronics. With atomically flat and dangling bond-free surfaces, hexagonal boron nitride (h-BN) has emerged as an ideal dielectric for graphene and related two-dimensional semiconductors. While high-quality, atomically thin h-BN has been realized via micromechanical cleavage and chemical vapor deposition, existing liquid exfoliation methods lack sufficient control over h-BN thickness and large-area film quality, thus limiting its use in solution-processed electronics. Here, we employ isopycnic density gradient ultracentrifugation for the preparation of monodisperse, thickness-sorted h-BN inks, which are subsequently layer-by-layer assembled into ultrathin dielectrics with low leakage currents of 3 × 10(-9) A/cm(2) at 2 MV/cm and high capacitances of 245 nF/cm(2). The resulting solution-processed h-BN dielectric films enable the fabrication of graphene field-effect transistors with negligible hysteresis and high mobilities up to 7100 cm(2) V(-1) s(-1) at room temperature. These h-BN inks can also be used as coatings on conventional dielectrics to minimize the effects of underlying traps, resulting in improvements in overall device performance. Overall, this approach for producing and assembling h-BN dielectric inks holds significant promise for translating the superlative performance of two-dimensional heterostructure devices to large-area, solution-processed nanoelectronics.

Solution-Processed Dielectrics Based on Thickness-Sorted Two-Dimensional Hexagonal Boron Nitride Nanosheets.

A well-defined insulating layer is of primary importance in the fabrication of passive (e.g., capacitors) and active (e.g., transistors) components in integrated circuits. One of the most widely known two-dimensional (2D) dielectric materials is hexagonal boron nitride (hBN). Solution-based techniques are cost-effective and allow simple methods to be used for device fabrication. In particular, inkjet printing is a low-cost, noncontact approach, which also allows for device design flexibility, produces no material wastage, and offers compatibility with almost any surface of interest, including flexible substrates. In this work, we use water-based and biocompatible graphene and hBN inks to fabricate all-2D material and inkjet-printed capacitors. We demonstrate an areal capacitance of 2.0 ± 0.3 nF cm–2 for a dielectric thickness of ∼3 μm and negligible leakage currents, averaged across more than 100 devices. This gives rise to a derived dielectric constant of 6.1 ± 1.7. The inkjet printed hBN dielectric has ...

All-2D Material Inkjet-Printed Capacitors: Toward Fully Printed Integrated Circuits

Characterization was performed on the application of atomic layer deposition (ALD) of hafnium dioxide (HfO2) and aluminum oxide (Al2O3), and plasma-enhanced chemical vapor deposition (PECVD) of silicon nitride (Si3N4) as metal–insulator–metal (MIM) capacitor dielectric for GaAs heterojunction bipolar transistor (HBT) technology. The results show that the MIM capacitor with 62 nm of ALD HfO2 resulted in the highest capacitance density (2.67 fF/μm2), followed by capacitor with 59 nm of ALD Al2O3 (1.55 fF/μm2) and 63 nm of PECVD Si3N4 (0.92 fF/μm2). The breakdown voltage of the PECVD Si3N4 was measured to be 73 V, as compared to 34 V for ALD HfO2 and 41 V for Al2O3. The capacitor with Si3N4 dielectric was observed to have lower leakage current than both with Al2O3 and HfO2. As the temperature was increased from 25 to 150 °C, the breakdown voltage decreased and the leakage current increased for all three films, while the capacitance increased for the Al2O3 and HfO2. Additionally, the capacitance of the ALD Al...

Characterization of atomic layer deposition HfO2, Al2O3, and plasma-enhanced chemical vapor deposition Si3N4 as metal–insulator–metal capacitor dielectric for GaAs HBT technology

The last decade has seen GaAs HBTs emerge as the dominant technology in wireless handset power amplifiers. Modern application requirements and size limitations have driven industry leaders towards the co-integration of depletion mode n-FET and GaAs HBT. The merger of Bipolar and FET, or BiFET, gives an additional degree of freedom in the design of advanced power amplifiers independent of a silicon controller. This paper provides an overview of the various techniques that can be used to join the two device technologies and then shows how a merged epitaxial structure, where an FET is formed in the emitter layers of an HBT, combines functional versatility with the high volume manufacturability needed to supply millions of power amplifiers at low cost. A large-signal model of the FET structure is developed which takes into account the unique physics and geometries of the device, including voltage-dependant parameters and charges on all four electrical terminals. Specific handset applications that can benefit or be enabled by BiFET are presented, such as on-off switching, low voltage bias controllers , Auto-Bias power amplifiers, and bias circuits with low or no voltage reference. When npn-only bias circuitry is limited to low voltage reference levels, HBT power amplifiers with BiFET bias stages are shown to have superior RF performance to their npn-only counterparts.

An InGaP/GaAs Merged HBT-FET (BiFET) Technology and Applications to the Design of Handset Power Amplifiers

Fabrication of a low resistivity tantalum nitride thin film

This paper covers the history and recent developments of GaAs BiFETs in commercial high volume GaAs HBT manufacturing environment. Further more, the paper also goes into “merged/stacked” FET-HBT integration schemes and their impacts on cost, yield and cycle time. Various circuit applications such as stage bypassing, attenuators, advanced bias circuit controls etc., that are realized in both BiFET approaches are also reviewed to show the commercial success of BiFET process technology. The challenges in using stacked FET-HBT geometry for an integrated transmit/receive switch and an alternative approach of utilizing advanced multi-chip module (MCM) techniques to deliver the same level of functionality in the smallest possible form-factor are examined with an emphasis on functional test yield and fabrication process yield.

Commercial Viability of a Merged HBT-FET (BiFET) Technology for GaAs Power Amplifiers

A gallium arsenide device (11) has a GaAs substrate (14) and a copper contact layer (21) for making electrical ground contact with a pad (16) of a target device. The copper contact layer is isolated from the GaAs substrate via a diffusion barrier layer (23), such as a nickel vanadium (NiV) layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. A gold or copper seed layer may be deposited prior to depositing the copper contact layer. The copper contact layer (21) can be directly soldered (18) to the contact pad (16), implying that the contact pad does not require an adhesive overflow area and can be made relatively small.

Ravi Ramanathan

Papers

Characterization of atomic layer deposition HfO2, Al2O3, and plasma-enhanced chemical vapor deposition Si3N4 as metal–insulator–metal capacitor dielectric for GaAs HBT technology

An InGaP/GaAs Merged HBT-FET (BiFET) Technology and Applications to the Design of Handset Power Amplifiers

Fabrication of a low resistivity tantalum nitride thin film

Commercial Viability of a Merged HBT-FET (BiFET) Technology for GaAs Power Amplifiers

Gaas integrated circuit device and method of attaching same