In order to design on-chip interconnect structures in a flexible way, a CAD approach is advocated in three dimensions, describing high frequency effects such as current redistribution due to the skin-effect or eddy currents and the occurrence of slow-wave modes. The electromagnetic environment is described by a scalar electric potential and a magnetic vector potential. These potentials are not uniquely defined, and in order to obtain a consistent discretization scheme, a gauge-transformation field is introduced. The displacement current is taken into account to describe current redistribution and a small-signal analysis solution scheme is proposed based upon existing techniques for static fields in semiconductors. In addition methods and apparatus for refining the mesh used for numerical analysis is described.

Method and apparatus for simulating physical fields

An electromagnetic field strength calculator calculates currents flowing through an electric circuit device which is an object of analysis by means of the moment method, and calculates and displays the strength of an electromagnetic field radiated from the electric circuit device from the calculated currents. In this calculator, a grid setup unit partitions a plane of a model representing the circuit device with a grid of lines having specified spacing. Next, a current calculation unit calculates currents at grid intersections or points within areas partitioned by the grid, on the basis of currents flowing through an element of the model of the circuit device calculated by means of the moment method. The currents thus calculated are displayed on a display by a current display unit. This allows a current at a point in the electric circuit device to be visually displayed in a form easy to understand.

Electromagnetic field strength calculator having function of displaying currents to be analyzed

The present invention evaluates the power dissipation of an electronic circuit. A power dissipation value is calculated for each transition or event generated during the electronic simulation of an electronic circuit design that corresponds to an actual electronic circuit. The present invention relies on data that includes an electronic circuit design description of the electronic circuit, such as a gate level netlist; a cell library having a power model corresponding to a cell instance; cell activity data such as net transitions; and the total effective load seen by each cell pin of the logic cell to be evaluated for power. The power model includes simple arcs (transition delay values, energy per arc values, cell input capacitances, and output slew rate values) and power evaluation data. The total energy dissipated by the cell during the modeled activity is calculated by determining the number of simple arcs applicable to the cell, attributing an energy dissipated for each arc, adding the energy values, and compensating for any double counting of short circuit and internal charge/discharge energy. Two fix-width queues are used by system as directed by the software code in the power evaluation tool. A queue may be defined in memory under program control but may be of any structure either in software or hardware. For each cell instance, power evaluation tool uses a first queue to track every transition and direction of the transition that occurs at an input pin, while a second queue is used to track every transition and direction of the transition that occurs at a boundary pin (i.e., an input pin or at an output pin). A power value for the cell instance may then also be obtained from the total energy dissipated during the modeled activity.

Efficient power analysis method for logic cells with many output switchings

A method for operating a computer to determine the electrical characteristics of a passive planar structure. The method starts by defining a first mesh on the structure. The first mesh divides the structure into polygons. A surface current is defined in the structure as a first weighted sum of a first set of basis functions. The weights of the first basis functions in the first weighted sum are calculated by solving Maxwell's equations. The mesh is then refined by dividing each polygon into a plurality of sub-polygons. The surface current in the sub-polygons is defined as a second weighted sum of a second set of basis functions. The second set of basis functions includes the first set of basis functions and a plurality of extension basis functions representing the additional degrees of freedom introduced by the refined mesh. The extension basis functions preferably include a capacitative set of basis functions representing the capacitative contribution of the sub-polygons and an inductive set of basis functions representing the inductive contributions of the sub-polygons. The contribution of each basis function in the capacitative and inductive sets of basis functions is estimated prior to solving Maxwell's equations in the refined level. Redundancy is eliminated by removing those capacitive basis functions whose contributions are less than a capacitative threshold value and those inductive basis functions whose contributions are less than an inductive threshold value.

Multi-resolution adaptive solution refinement technique for a method of moments-based electromagnetic simulator

An electronic device simulator includes a three-dimensional lumped device model, a three-dimensional visco-elastic process simulation model and a material design model that are interlinked with each other. The three-dimensional lumped device element model comprises a Poisson's equation model, an electron continuity equation model, a hole continuity equation model, a Maxwell's equations model, an eddy current equation model, and an Ohm's law equation model. The simulator accounts for the three dimensional characteristics of the circuit to determine circuit performance.

Method and apparatus for simulating manufacturing, electrical and physical characteristics of a semiconductor device

A method of controlling a circuit simulator for examining the electromagnetic behaviour of an electrical conductor pattern is based on reducing the equivalent circuit model of the pattern. The pattern is first represented by a collection of geometrical elements, whose size is determined by the scale of the geometrical details that is well below the minimum wavelength contemplated. Selection of a set of those elements that lie approximately at a distance of one wavelength from one another and expressing the field values of the non-selected elements in terms of the field values for the selected elements permits correlating a low rank admittance matrix and the matrices of the Maxwell equations. Typically, an effective reduction of four orders of magnitude in the number of equivalent circuit components is obtained without losing model accuracy.

Rene Du Cloux

Papers

PCB simulation on basis of reduced equivalent circuit