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Ricardo P. Jasinski
Researcher at Federal University of Technology - Paraná
Publications - 15
Citations - 188
Ricardo P. Jasinski is an academic researcher from Federal University of Technology - Paraná. The author has contributed to research in topics: Efficient energy use & Energy consumption. The author has an hindex of 6, co-authored 15 publications receiving 157 citations.
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Journal ArticleDOI
Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded Systems
Eduardo Viegas,Altair Olivo Santin,André Luiz Pereira de França,Ricardo P. Jasinski,Volnei A. Pedroni,Luiz S. Oliveira +5 more
TL;DR: It is demonstrated that a hardware (HW) implementation of network security algorithms can significantly reduce their energy consumption compared to an equivalent software (SW) version.
Proceedings ArticleDOI
Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs
TL;DR: The approach takes advantage of existing low-voltage differential signalling I/O pads, which allows the implementation of low-cost ADCs into existent FPGAs, even though such digital devices do not possess analog interfacing capabilities at first.
Journal ArticleDOI
A reliable and energy-efficient classifier combination scheme for intrusion detection in embedded systems
Eduardo Viegas,Altair Olivo Santin,Luiz S. Oliveira,André Luiz Pereira de França,Ricardo P. Jasinski,Volnei A. Pedroni +5 more
TL;DR: This paper presents an anomaly-based method for network intrusion detection in embedded systems that maintains the classifier reliability even when network traffic contents changes and is energy-efficient and well suited for hardware implementation.
Proceedings ArticleDOI
Moving Network Protection from Software to Hardware: An Energy Efficiency Analysis
TL;DR: This paper presents a new way to improve the throughput and to reduce the energy consumption of an anomaly-based intrusion detection system for probing attacks, and implements the same classifier algorithm in software (C++) and in hardware (synthesizable VHDL).
Proceedings ArticleDOI
A new hardware coprocessor for accelerating Notification-Oriented applications
TL;DR: A new hardware coprocessor is created that is able to run existing NOP applications and provided a decrease of 96% in the number of clock cycles, compared to a purely software implementation.