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Ricardo Tapiador-Morales

Researcher at University of Seville

Publications -  26
Citations -  448

Ricardo Tapiador-Morales is an academic researcher from University of Seville. The author has contributed to research in topics: Neuromorphic engineering & Field-programmable gate array. The author has an hindex of 7, co-authored 26 publications receiving 310 citations. Previous affiliations of Ricardo Tapiador-Morales include University of Zurich.

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Journal ArticleDOI

NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps

TL;DR: In this article, the sparsity of neuron activations in CNNs is exploited to accelerate the computation and reduce memory requirements for low-power and low-latency application scenarios.
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Wireless Sensor Network for Wildlife Tracking and Behavior Classification of Animals in Doñana

TL;DR: A hierarchical, wireless sensor network installed in Doñana National Park is proposed, to collect information about animals' behaviors using intelligent devices placed on them which contain a neural network implementation to classify their behavior based on sensory information.
Journal ArticleDOI

Embedded neural network for real-time animal behavior classification

TL;DR: This work presents an animal behavior recognition, classification and monitoring system based on a wireless sensor network and a smart collar device, provided with inertial sensors and an embedded multi-layer perceptron-based feed-forward neural network, to classify the different gaits or behaviors based on the collected information.
Journal ArticleDOI

Neuromorphic LIF Row-by-Row Multiconvolution Processor for FPGA

TL;DR: Inspired in the leaky integrate-and-fire (LIF) neuron, an event-based field-programmable gate array (FPGA) multiconvolution system is proposed, its main novelty is the combination of a memory arbiter for efficient memory access to allow row-by-row kernel processing.
Posted ContentDOI

Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification

TL;DR: A VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation DVS retina to obtain a normalized histogram to be used by a particular CNN accelerator, called NullHop is presented.