Showing papers by "Richard Hartley published in 1990"

Digit-serial processing techniques

Abstract: An architecture is presented for hard-wired data-flow algorithms which is based on the transmission of arithmetic data one digit at a time serially, and performance of operations digit-serially on that data. It is shown that digit-serial computation gives rise to particularly efficient chip designs, and that choice of digit-size allows the user to match throughput requirements to specifications. Details of the implementation of the individual operators as a cell-library of silicon CMOS circuits are given and mention is made of the software environment (silicon compiler) which allows the rapid translation of algorithms to integrated circuits. >

Recursive computation of the Fourier transform

Abstract: Efficient recursive methods and circuits for computing a continuously updated discrete Fourier transform (DFT) of an input-digital signal are considered. The Fourier transform (FT) is recomputed at each sample input time, with only O(N) operations being required to compute the transform, where N is the number of frequency bins. Various window functions are considered for windowing the input-wave form, namely a rectangular window, a triangular window, and an exponential window. The last type of window has not been widely considered in the past, partly due to its asymmetrical shape, and hence nonlinear phase response. Nevertheless, it is shown to have certain advantages in ease of computation and in flexibility. For the exponential window, a circuit that conveniently allows zooming in to particularly interesting parts of the frequency spectrum is shown. By appropriately loading a multiplier storage RAM, arbitrarily fine resolution may be achieved in any part of the spectrum, thus permitting closely adjacent peaks to be distinguished. The general approach is based on the interpretation of the FT as a set of simultaneous bandpass filters. Though these filters are generally finite-impulse-response filters, computational advantages are derived from formulating them as recursive filters. >

Measuring velocity of a target by Doppler shift, using improvements in calculating discrete Fourier transform

Abstract: The invention is embodied in improvements in calculating discrete Fourier transform (DFT) using recursive digital filtering in a method for determining the velocity of a target located in a medium for vibratory energy. In the method a transmitter electrical signal of prescribed frequency is generated. Coherent vibratory energy, the frequency of which is in fixed relationship with said prescribed frequency, is transmitted into the medium and is directed toward the target. The transmitting is done in recurring pulses of prescribed duration. During range gate intervals each of prescribed duration, the transmitted coherent vibratory energy is received from the medium after its interaction with the target. The vibratory energy which is received during the range gate intervals is converted to a receiver electrical signal. The transmitter and receiver electrical signals are mixed together to obtain a demodulated electrical signal through heterodyning or homodyning. The demodulated electrical signal is digitized and then digitally filtered on a recursive basis to separate it into digitized spectral components in accordance with a discrete Fourier transform procedure. Squaring the absolute value of each of the digitized spectral components generates digital electric signals descriptive of the power spectrum of the interaction of the vibratory energy with said target. After performing a comparative analysis of the digital electric signals descriptive of that power spectrum, the velocity of the target is calculated from the results of the comparative analysis.

A new simultaneous circuit partitioning and chip placement approach based on simulated annealing

Abstract: The problems of circuit partitioning and chip placement have been studied in the past Given a circuit partitioned into chips, one can optimize the placement of the chips on a printed circuit board with regard to a given cost function Conversely, given a placement of the chips on the board, one can optimize the partitioning of the circuit into the chips with regard to the same cost function However, given neither the circuit partitioning nor the chip placement, we are faced with a difficult optimization problem Our target technology is one in which the chips are unpackaged chips placed on a substrate, analogous to the printed circuit board and interconnected together with high density interconnect to realize a complex system We propose a new approach in which the circuit is both partitioned and placed simultaneously by a simulated annealing based algorithm Our approach is seen to yield excellent results in reasonable run times

Increased performance of digital integrated circuits by processing with multiple-bit-width digits

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Data format converters for use with digit-serial signals

Abstract: Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

Digit-serial transversal filters

Abstract: One type of transversal filter using digit-serial signals in its operation comprises a to-digit-serial converter for converting a succession of input data words received at its input port each to a respective succession of m-bit-wide digits supplied from its output port in order of progressively greater significance, m being a positive plural integer; a clocked delay line having an input tap connected for responding to the m-bit-wide digits supplied from the output port of the to-digit-serial converter and having at least one further tap for supplying a respective tap signal; and means for performing a weighted summation of the input signal to the clocked delay line and each tap signal from the clocked delay line, to generate a filter response in digit-serial format. Another type of transversal filter, which uses digit-serial signals in its operation, comprises a plurality, p in number, of parallel-to-digit-serial converters, each for generating a respective m-bit-wide digit-serial data stream by converting n-parallel-bit words in an input signal to the digital filter, m being a positive integer and n being the product of m and p; a plurality of tapped delay lines having respective input taps connected from respective ones of said parallel-to-digit-serial converters and each having at least one further tap; means for generating p different phases of filter response in digit-serial form by weighting and summing digital signals taken from respective taps on ones of the p tapped delay lines; and p digit-serial-to-parallel converters for converting, on a cyclic basis, the different phases of filter response to parallel-bit words in an output signal from the digital filter.

Internal test circuitry for integrated circuits using token passing to select testing ports

Abstract: Built-in test circuitry, which is appropriate for monolithic integrated circuit chips that are to be connected in a plural-chip package, uses electronic token passing to select one of the test input ports in the circuitry to be tested for application of test input vectors. The built-in test circuitry also uses electronic token passing to select one of the test output ports in the circuitry to be tested from which test results are to be supplied.

Computation of discrete fourier transform

Abstract: The discrete Fourier transform is continuously calculated at input signal sample rate using recursive filtering, rather than transversal filtering. This reduces the number of complex digital multiplications per computational cycle to N, the number of spectral components in the discrete Fourier transform, where rectangular truncation window or a new exponential window is used. Where a triangular truncation window is used the number of complex digital multiplications per computational cycle is reduced to 2N.

Digit-serial recursive filters

Abstract: A recursive digital filter for digit-serial signals comprises a digit-serial adder having an augend input port to which successions of m-bit-wide digits of a digital-serial filter input signal are supplied in order of progressively greater significance, having at least a first addend input port, and having a sum output port; digit-serial multiplier apparatus having a multiplicand input port connected from the sum output port of said digit-serial adder and having a product output port for supplying a weighted response to signal received at its multiplicand input port; and means for applying the weighted response to the first addend input port of the digit-serial adder so as to be in word alignment with the digit-serial input signal to the augend input port of the digit-serial adder. In various filtering systems the recursive digital filter for digit-serial signals is preceded by a to-digit-serial converter to convert digit-serial format input signal supplied in a different digital signal format, is succeeded by a from-digit-serial converter to convert the digit-serial filter response to a different digital signal format, or is both preceded by a to-digit-serial converter and succeeded by a from-digit-serial converter.

Rapid prototyping using high density interconnects

Abstract: This paper introduces the discretionary interconnect one-day electronic systems (DIODES) for the rapid prototyping of DSP electronic systems. DIODES merges silicon compiler and high-density interconnect technology with the goal of prototyping hardware systems as quickly as possible-within one day. Working from a high-level algorithmic description of a DSP algorithm, DIODES will determine which chips from an inventory of specially designed chips are needed to implement the design. These chips are then placed on a prepared substrate and routed together using computer controlled laser lithography to produce a hardware implementation of the design. >

Testing of integrated circuits including internal test circuitry and using token passing to select testing ports

Abstract: Built-in test circuitry, which is appropriate for monolithic integrated circuit chips that are to be connected in a plural-chip package, uses electronic token passing to select one of the test input ports in the circuitry to be tested for application of test input vectors. The built-in test circuitry also uses electronic token passing to select one of the test output ports in the circuitry to be tested from which test results are to be supplied. Methods for testing based on these token passing procedures are described.

A synthesis, test and debug environment for rapid prototyping of DSP designs

Abstract: Recently, considerable progress has been made in the design of digital signal processing (DSP) integrated circuits and systems. In order to address the need for rapid and economical production and testing of hardware prototypes, a hardware and software system called DIODES is being developed for the rapid prototyping, testing and debugging of DSP designs. DIODES will allow the user to design a DSP system, have it partitioned into predefined function blocks, have it assembled using advanced packing technology and then thoroughly test and debug the design both stand-alone and in a larger electronic system environment. This paper gives an overview of the whole system focussing particularly on the debugging hardware and software support environment. The algorithmic description is translated by the DIODES synthesis software into a structural specification suitable for High-Density Interconnect (HDI) fabrication. The synthesis process includes the insertion of test capabilities into the hardware to allow for debugging the design. The rapid turnaround of HDI fabrication means that the user can have a prototype DIODES module in hand ready for testing within at most a day or two, and at moderate cost. >

Use of digit-serial computation in systolic arrays

Abstract: A method is described whereby digit-serial computation can be applied in a fairly general way to a class of systolic arrays so as to cut down substantially the amount of hardware used. Rather than increasing the utilization of the standard processor hardware, the technique proposed allows throughput to be maintained while reducing the hardware by a factor approaching alpha . The technique is to divide the data words into alpha sections, or digits, and to process these digits serially. Digit-serial data inherently have a data rate that is an integer submultiple of the parallel data rate, and the digit-size can be chosen so as to meet the data rates required by the systolic algorithm. The advantages of this approach are twofold: the number of wires required for the transmission of data is decreased and the computational elements can be smaller (digit-serial computational elements replacing the standard parallel operators). Thus, the computational elements are fully utilized. >

Rapid prototyping of electronic systems

Abstract: Describes a system for the rapid prototyping, testing and debugging of DSP designs. The DSP algorithm is first coded in a high level algorithmic language. This description is translated by the synthesis software into a structural specification suitable for HDI fabrication. The synthesis process includes the insertion of test capabilities into the hardware to allow for debugging the design. The rapid turnaround of HDI fabrication means that the user can have a prototype HDI module (DSP accelerator) in his hands ready for testing within at most a day or two, and at moderate cost. The DSP accelerator is then placed in a socket on a specially designed board (called the mother-board), connected to a Sun or other workstation, where it may be thoroughly tested and debugged. The debugging capabilities include structural verification, debugging and in-system test. Structural verification is testing the DSP accelerator to see that it is connected together correctly and that all the parts are working. Debugging involves sending test vectors through the chip, stepping, observing internal node values and limited reconfigurability with the purpose of debugging the algorithm. In-system test is done by connecting the DSP accelerator via a cable into the target system. This allows the system to be run at full speed (up to 20 MHz) with the DSP accelerator in place, but still retaining full observability of internal nodes. >

A testing methodology for large scale hybrid VLSI

Abstract: A test methodology for large systems-on-a-chip designed by the Discretionary Interconnect One Day Electronic System (DIODES) system for the rapid prototyping of digital signal processing (DSP) electronic systems is discussed. DIODES is based on the concept of building a library of chips that implement a set of operators used in DSP algorithms, and using these chips to implement DSP algorithms by implanting them on an alumina substrate and interconnecting them appropriately to realize the desired functionality. Test hardware capabilities are discussed. A description of test circuitry is given. The test methodology is compared with boundary scan. >