An apparatus and method are provided for virtual memory mapping and transaction management in an object-oriented database system having permanent storage for storing data in at least one database, at least one cache memory for temporarily storing data, and a processing unit which runs application programs which request data using virtual addresses. The system performs data transfers in response to memory faults resulting from requested data not being available at specified virtual addressed and performs mapping of data in cache memory. The data in the database may include pointers containing persistent addresses, which pointers are relocated between persistent addresses and virtual addresses. When a data request is made, either for read or write, from a given client computer in a system, other client computers in the system are queried to determine if the requested data is cached and/or locked in a manner inconsistent with the requested use, and the inconsistent caching is downgraded or the transfer delayed until such downgrading can be performed.

Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system

An object code expansion program inserts new instructions and data between preexisting instructions and data of an object code file; offsets are modified to reflect new positions of the preexisting instructions and data. For each item of preexisting object code (instructions or data), the following steps are performed: making a new code block comprising any desired new instructions and the item, and storing it as new object code; tracking the location of the item and the new code block within the new object code; and tracking items that contain inter-item offsets. Then, each inter-item offset is updated using the new location of the item or new code block, as required. Finally, offsets in symbol tables and relocation structures are updated with the new location of the item. This expansion program is used to add instructions to object code files of a second program, to monitor substantially all of the memory accesses of the second program. The added instructions establish and maintain a memory status array with entries for memory locations that are validly accessible by the second program; entries indicate the status of corresponding memory locations. The memory status array is used to check for the errors of writing to unallocated memory and reading from unallocated or uninitialized memory. Also, the data section of the object code files are expanded with extra dummy entries to aid in the detection of array bounds violations and similar data errors. Furthermore, watchpoints can be established for more comprehensive monitoring.

Method and apparatus for modifying relocatable object code files and monitoring programs

A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.

Cache coherency protocol for multi processor computer system

A computer system includes processor having dual execution cores and a non-volatile memory that stores an error recovery routine. The processor's execution cores operate in lock step when the processor is in a redundant execution mode, and they operate independently when the processor is in a split execution mode. The error recovery routine is invoked when the processor detects a soft error while operating in the redundant execution mode. The error recovery routine switches the processor to split execution mode. In split mode, each execution core saves uncorrupted processor state data to a designated memory location and updates any corrupted data with corresponding processor state data from the other execution core. The error recovery routine returns the processor to redundant mode, initializes each execution core with the recovered processor state data, and returns control of the processor to the program thread that was executing when the soft error was detected.

Firmware mechanism for correcting soft errors

A multiprocessor digital data processing system comprises a plurality of processing cells (18A to 18R, 34A to 34F, 38A, 38B) arranged in a hierarchy of rings (12A to 12F, 14A and 14B, 16). The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Multiprocessor digital data processing system

A multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory (PD). Each PD has a plurality of line entries which define the content of corresponding line positions in the associated SIC. Each line entry has an associated data shareability control bit, designated EX, which may be set to a one or zero state to indicate, respectively, the exclusive (EX) or readonly (RO) state of the associated line. An exclusive line is not shareable, but a readonly line is shareable i.e. may exist validly in more than one SIC in the MP. Any CP in the MP can request data in an EX state from its SIC, which data may or may not be found in its SIC or in another CP's SIC. If a CP requests a line of storage data in EX state and the line is found in EX state in another CP's SIC, it may be allowed to remain in the other CP's SIC by being set to RO state in both CPU SICs for the situations in which: (1) the line is found unchanged in EX state in the other CP's SIC, or (2) the line is found in RO state in the other CP's SIC, in which case the line is received and set to RO state in the requesting SIC even though requested in EX state. But if the line is found to be changed in the other CP's SIC, its shareability designation in the requesting SIC will be EX and the line is invalidated in the other CP's SIC from where it is castout.

Cache storage line shareability control for a multiprocessor system

Error detection and recovery is provided in a processor of small size and which can be integrated on a single chip by providing buffers for both data and processor status codes in order to contain errors until a subsequent check point preferably generated at the termination of each instruction is reached without detection of an error. Retry of an instruction can therefore be initiated using the status and data validated at the termination of the previous check point and without placing error correction processing in any critical path of the processor. Error detection is accomplished by comparing outputs of at least a pair of unchecked processors for both memory access requests and output data and status codes. Input to the processors is subjected to a parity check and parity check bits are generated for memory access requests. Error correcting codes are generated for data and status codes to allow correction of single bit errors during transmission within the processor or at a storage system. When an error is detected, all data which has not been validated, preferably by changing the logical value of a flag bit associated with each code, at the most recently generated check point is erased. Data codes in which the flag bit has been changed may be transferred to a storage system autonomously even after an error has occurred.

Data processor with enhanced error recovery

In a multiprocessor (MP) system each processor (CP) has an associated store-in-buffer cache (BCE) whose set-associative classes (lines) are designated exclusive (EX) or shareable by all processors (RO). The cache directories (PD) are addressed by the non-translatable address part and by some bits of the translatable address part so that cache synonyms occur. Accesses of a processor to its cache are either flagged exclusive (EX) for store instructions and operand fetches or shareable (RO) for instruction fetches. To reduce the number of castouts in case of cache conflicts the shareability of a new cache line brought in after a cache miss is determined from its original shareability, the type of access to be performed and the change status of the line. An exclusive (operand) fetch to a cache line a copy of which is in a remote processor and designated exclusive is changed to RO if no changes have been made to that line. A synonym designated RO in the processors own cache is, duplicated to speed up further accesses. Synonym detection in all caches is performed in parallel by permuting the translatable address bits. For faster operation each processor has a further cache directory (CD) which is used for synonym detection and cross-interrogation.

Richard N. Gustafson

Papers

Cache storage line shareability control for a multiprocessor system

Data processor with enhanced error recovery

Cache storage hierarchy for a multiprocessor system