An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Plastic integrated circuit package and method and leadframe for making the package

An ultra-thin level-one integrated circuit package with improved moisture penetration characteristics manufactured using a transfer molded casing with metallic lamination layers is provided. Additionally, a method and apparatus for providing a multiple-element modular package including a plurality of such level-one packages in horizontal or vertical stack configuration is provided.

Ultra high density integrated circuit packages method

A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.

Semiconductor connection components and methods with releasable lead support

A molded plastic package for semiconductor devices incorporating a heat sink, controlled impedance leads and separate power and ground rings is described. The lead frame of the package, separated by a dielectric layer, is attached to a metal heat sink. It has more than one ring for power and ground connections. The die itself is attached directly onto the heat sink through a window on the dielectric and provides high power dissipation. The package is molded using conventional materials and equipment.

Molded plastic package with heat sink and enhanced electrical performance

An improved package for semiconductor chips, and method of forming the package are provided. The package includes a lead frame having a central chip bonding portion and first and second sets of interdigitaled fingers. The inner ends of the first set of fingers terminate at a distance from the central chip bonding portion closer than the inner ends of the fingers of the second set at fingers. A semiconductor chip, having input/output pads is bonded to the central chip bonding portion. A first set of wires directly couples respective input/output pads on the chip to the first set of fingers. A second set of wires couples respective input/output pads on the chip with the second set of fingers. Each of the wires of the second set of wires has a first segment extending from its respective input/output pad to an intermediate bonding region, and a second segment extending from the intermediate bonding region to its respective finger of the second set of fingers.

Lead frame-chip package with improved configuration

According to the present invention, an improved chip and leadframe package assembly and method of making the same is provided. The package assembly is comprised of a metal leadframe having a chip bond pedestal centrally located and a plurality of discrete leads surrounding the pedestal. An I/C (integrated circuit) semiconductor chip is mounted on the pedestal, the chip having a plurality of connection or bonding pads disposed around the periphery. An interposer having a layer of dielectric material and discrete metal lines formed thereon is mounted on an apron of the chip bonding pedestal between the location of the chip and the inner discrete leads of the leadframe. Connections are provided between the bonding pads on the chip and the respective lines on the interposer and connections are also provided between the fingers and the respective lines on the leadframe. Additionally, the interposer also preferably includes at least one voltage bus line formed thereon having a portion adjacent at least one edge of the chip for connection of any of the chip bond pads thereto. Further, the pedestal also preferably includes radially extending conducting arms suitable for providing both electrical ground connection and a heat dissipation path.

High performance versatile thermally enhanced IC chip mounting

Multiple, single conductor, tape automated bonding (TAB) tapes (36, 37, 38) are sequentially applied to a semiconductor device (31) by the bonding of a first, etched, single layer TAB tape to an outer row of bonding pads (32, 33, 34) on a semiconductor chip and to selected contacts on a lead frame followed by the laying down of at least one additional etched, single layer TAB tape which is then bonded to an inner row of bonding pads on the semiconductor chip and to different selected lead frame contacts. If desired the subsequent TAB tape may be adhered to the preceding TAB tape to increase the mechanical strength of all the tapes and improve the electrical characteristics of the tapes. The application of one or more ground planes to the assembly is also shown.

Tape bonded semiconductor device

A compliant lead for electromechanically surface mounting an integrated circuit chip package to a substrate. The compliant lead extends from the package and includes at least two regions of different lead thickness. In a first region, a standard lead thickness is employed to ensure the applicability of existing package fabrication techniques. A second region, having a reduced thickness, then extends from the first region and is predefined to encompass an area of the lead expected to undergo greatest stress during thermal cycling. Compliancy is further guaranteed by providing a solder dam within the region of reduced thickness to limit wicking of solder when the package is solder mounted to the substrate. Lead frame fabrication is also discussed.

Compliant lead for surface mounting a chip package to a substrate

A method of packaging an electronic module in a cap is disclosed. The module, comprising one or more silicon chips mounted on a substrate and having the chips sealed onto the substrate with a silicone polymer is supported on a cap with the chips disposed inwardly. An epoxy is dispensed on the back surface of the substrate and allowed to flow and bridge over the gap between the substrate and cap. The epoxy is cured by first heating the assembly with the applied epoxy to a temperature which will gel the epoxy. The temperature and rate of heating are selected so that the temperature is stabilized before the critical viscosity of the epoxy is reached. Subsequently, a higher temperature is used to complete the cure. The process is also characterized in that no significant decrease in temperature is permitted after the dispensing and flowing of the epoxy.

Richard W Noth

Papers

Lead frame-chip package with improved configuration

High performance versatile thermally enhanced IC chip mounting

Tape bonded semiconductor device

Compliant lead for surface mounting a chip package to a substrate

Method of sealing an electronic module in a cap