A system for adaptively bypassing one or more higher cache levels following a miss in a lower level of a cache hierarchy is described. Each cache level preferably includes a tag store containing address and state information for each cache line resident in the respective cache. When an invalidate request is received at a given cache hierarchy, each cache level is searched for the address specified by the invalidate request. When an address match is detected, the state of the respective cache line is changed to the invalid state, although the address of the cache line is left in the tag store. Thereafter, if the processor or entity associated with this cache hierarchy issues its own request for this same cache line, the cache hierarchy begins searching the tag store of each level starting with the lowest cache level. Since the address of the invalidated cache line was left in the respective tag store, a match will be detected at one of the cache levels, although the corresponding state of this cache line is invalid. This condition is specifically detected and is considered to be an “inval_miss” occurrence. In response, to an inval_miss, the cache hierarchy calls off searching any higher levels, and instead, issues a memory reference request for the desired cache line. In a further embodiment, the entity that sourced an invalidate request is stored, and a subsequent memory reference request for the same cache line is sent directly to the source entity.

Method and apparatus for adaptively bypassing one or more levels of a cache hierarchy

A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory subsystem, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

Distributed data dependency stall mechanism

A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system

A method and apparatus for arbitrating access to a selected device in a computer system comprises a routine for registering access rules for accessing the selected system device, a plurality of competing clients which may each request a connection to the selected device, and an arbitrator which uses the registered access rules to negotiate access to the requested connection on behalf of the competing clients.

Method and apparatus for arbitrating access to selected computer system devices

The invention provides a system and method for resolving ambiguous invalidate messages received by an entity of a computer system. An invalidate message is considered ambiguous when the receiving entity cannot tell whether it applies to a previously victimized memory block or to a memory block that the entity is waiting to receive. When an entity receives such an invalidate message, it stores the message in its miss address file (MAF). When the entity subsequently receives the memory block, the entity “replays” the Invalidate message from its MAF by invalidating the block from its cache and issuing an Acknowledgement (Ack) to the entity that triggered issuance of the Invalidate message command.

Mechanism for resolving ambiguous invalidates in a computer system

A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus

A shared memory multiprocessor computer system in which one or more processor modules and/or input/output modules have cache memories. The main memory controller for each main memory of the system maintains a duplicate cache tag array containing current information on the status of data lines from the main memory that are stored in the cache memories. Thus, coherency checks can be performed directly by the main memory controller. This eliminates the need for each processor having a cache memory to perform a separate coherency check and to communicate the results of its coherency checks to the main memory controller, and thereby reduces delays associated with processing coherent transactions.

Cache tag system for use with multiple processors including the most recently requested processor identification

A shared bus system (100) having a bus (112) and a set of client modules (116, 120) coupled to the bus (112). Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue (164, 168) for storing transactions received by the module for processing. A bus controller (114) limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.

Queue-based predictive flow control mechanism

A bus system (10) having a bus arbitration schemeincludes a bus (12) and a plurality of client modules (16, 18, 20, 22, 24, 26) coupled to the bus (12), each of the client modules being capable of transmitting information on the bus (12) to another of client module, and only one client module being entitled to transmit information on the bus (12) at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module (14) that informs the client modules what types of transactions allowed on the bus in a given cycle. Each arbitration signal processor preferably is also responsive to the client option signals sent by the host module during an earlier cycle.

Fast pipelined distributed arbitration scheme

A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.

Robert D. Odineal

Papers

Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus

Cache tag system for use with multiple processors including the most recently requested processor identification

Queue-based predictive flow control mechanism

Fast pipelined distributed arbitration scheme

Queue-based predictive flow control mechanism with indirect determination of queue fullness