Patent
Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
Craig R. Frink,William R. Bryg,Kenneth K. Chan,Thomas R. Hotchkiss,Robert D. Odineal,James B. Williams,Michael L. Ziegler +6 more
TLDR
In this paper, the authors propose a coherency scheme for a system having a bus, a main memory, and an access controller for accessing main memory in response to transactions received on the bus.Abstract:
A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.read more
Citations
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References
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Patent
Consistency protocols for shared memory multiprocessors
TL;DR: In this paper, the authors propose a Consitency Protocol for Shared Memory Multi-Processor (CMMC) which allows the caches to store multiple copies of read/write data at identical physical addresses for use by the respective processors.
Patent
Arbitration means for controlling access to a bus shared by a number of modules
David L. Budde,David G. Carson,Stephen R. Colley,David B. Johnson,Robert P. Voll,Doran Wilde +5 more
TL;DR: In this paper, an arbitration mechanism comprising a request FIFO (408) for storing ones and zeros corresponding to received requests in the order that they are made is presented.
Patent
Method and apparatus for distributed queue multiple access in a communication system
TL;DR: In this article, a distributed queue multiple access (DMA) scheme is proposed for a system comprising two counter-flowing transmission busses (A,B), plural stations (i, j) connected between them, and a head-end station generating slots on the first one (A) of the bussedes; each station transmitting access requests on the second one (B), and determining its right to transmit data in slots on first bus on the basis of access requests it has seen.
Patent
Read in process memory apparatus
Keeley James W,Barlow George J +1 more
TL;DR: In this article, a cache memory subsystem couples to main memory through interface circuits via a system bus in common with a plurality of central processing subsystems which have similar interface circuits, including multilevel directory memory and buffer memory pipeline stages shareable by at least a pair of processing units.
Patent
Multiprocessor cache examiner and coherency checker
TL;DR: In this article, a cache examining protocol is proposed for a multiprocessor RISC system, which enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states.