https://digital.library.unt.edu/ark:/67531/metadc1091677/m2/1/high_res_d/5549333.pdf

Semiconductor drift chamber: an application of a novel charge transport scheme

The pinned photodiode is the primary photodetector structure used in most CCD and CMOS image sensors. This paper reviews the development, physics, and technology of the pinned photodiode.

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A Review of the Pinned Photodiode for CCD and CMOS Image Sensors

CMOS based imagers are beginning to compete against CCDs in many areas of the consumer market because of their system-on-a-chip capability. Sensitivity, however, is a main weakness of CMOS imagers and enhancements and deviations from standard CMOS processes are necessary to keep up sensitivity with downscaled process generations. In the introductory section several definitions for the sensitivity of image sensors are reviewed with regard to their potential to allow meaningful comparison of different detector structures. In the main section, the standard CMOS sensor architecture is compared to detector structures designed to improve the sensitivity, namely the photogate (PG), the pinned photodiode (PPD) and the thin film on ASIC (TFA) approach. The latter uses a vertical integration of the photodiode on top of the pixel transistors. A careful analysis of the relevant electrical, optical and technological parameters and many previously published experimental data for different imagers reveals that only the PPD and the TFA enhancements provide satisfactory sensitivity and withstand scaling down to 0.18 /spl mu/ processes. Due to the higher fill factor and the higher quantum efficiency TFA provides significantly better values than PPD. The radiometric sensitivity of a 5 /spl mu/m/spl times/5 /spl mu/m TFA pixel is found to amount to 11.9 V/(/spl mu//cm/sup 2/) for a 0.25 /spl mu/m process and 27.5 V/(/spl mu/J/cm/sup 2/) for a 0.18 /spl mu/m process.

Sensitivity of CMOS based imagers and scaling perspectives

The effects of bulk traps on the transfer effciency and transfer noise in bulk channel charge-coupled devices (BCCD's) are calculated for different charge packet sizes and operating frequencies. These predictions are compared with experimental results and the distribution and density of bulk states in actual devices are thereby measured. The measured low transfer inefficiency of 10-4per transfer with no intentionally introduced background charge and low transfer noise are shown to be due to a low bulk state density of 2 × 1011/cm3. A detailed comparison of estimated noise in both surface and bulk channel versions of an image sensor and an analog delay line show that BCCD's are very attractive for low-light level imaging but not as attractive for analog signal processing.

II-3 the effects of bulk traps on the performance of bulk channel charge-coupled devices

Population counting is performed by using a multiplying unit, in the computer system, including a plurality of multiplying sub-units for simultaneously executing partial multiplication among elements obtained by dividing a multiplicand data and a multiplier data in a regular multiplication mode. In a population counting mode, an input data for the population counting is divided into population counting elements instead of the multiplier data and population counting on the population counting elements are performed simultaneously using the multiplying sub-units which produce partial counted data of the population counting elements, and the partial counted data is sent to a carry save adder and a carry propagate adder by which a population counting result for the input data is obtained and output.

Multiplying unit in a computer system, capable of population counting

The charge-coupled device, as described originally by Boyle and Smith,1 operates by moving minority carriers along the surface of a semiconductor with voltage pulses applied to metal electrodes which are separated from the semiconductor by an insulating layer. The transit from one electrode to the next is determined by the minority carrier transport under the influence of their own potential, fringing fields, and diffusion, and by the trapping properties of interface states. The transport limitations are largely determined by device geometry;2 for 10-μm electrodes, thermal diffusion is predominantly responsible for transferring the last small amounts of charge forward and limits efficient operation to clock frequencies below 10 MHz. Surface state trapping is much less dispersive, and even at low frequencies 1011 states/cm2 eV can impose the requirement for regeneration after as few as 100 transfers.3,4 In order to circumvent these problems, Boyle and Smith5 have proposed a modified CCD structure in which the charges do not flow at the semiconductor surface; instead they are confined to a channel which lies beneath the surface. This buried channel device has the potential of eliminating surface state trapping. (Bulk trapping should be several orders of magnitude less important as a CCD loss mechanism.) Calculations show that this modification will give rise to increased fringing fields under the CCD electrodes. Diffusion is replaced as an important factor in the intrinsic transfer process by the more powerful field-aided transfer. This leads to fast, efficient transport even when very little charge remains to be transferred. In addition to these advantages, the higher mobility found in the bulk of the semiconductor should further enhance the speed of the device.2

B.S.T.J. brief: The buried channel charge coupled device

To ensure predictable directionality of charge transfer in twophase charge coupled devices (CCD''S), the potential well associated with each half-bit must be asymmetrical so as to enhance charge transfer in the desired direction and to inhibit transfer in undesired directions. In the instant invention, localized portions of immobile charge are disposed under the CCD electrodes and, advantageously, offset with respect to the centers of the electrodes so that suitably asymmetrical potential wells are formed when a suitable voltage is applied to the electrodes. In a presently preferred embodiment, the immobile charge is provided by relatively highly doped surface zones in a semiconductor bulk portion of relatively low doping.

Charge coupled devices employing nonuniform concentrations of immobile charge along the information channel

A circuit for rotating a multibit binary word in either the right or the left direction includes a scale factor decoder receiving a scale factor word which specifies the magnitude of the rotation and a direction control signal which specifies the direction of rotation and providing a shift control word which is the same as the scale factor word when a right rotation is specified but providing a shift control word which is the complement of the scale factor word when a left rotation is specified. The circuit also includes a plurality of input buffers receiving an input word and providing corresponding input data, and a one-bit rotator receiving the input data and the direction control signal and rotating the input data in the right direction by one position when a left rotation is specified or providing the input data without rotation when a right rotation is specified. In addition, the circuit includes a network receiving data from the one-bit rotator and the shaft control word and rotating the data from the one-bit rotator in only the right direction by a magnitude specified by the shift control word. Furthermore, the circuit includes a plurality of output buffers receiving the data from the network and providing an output word.

Data shifting and rotating apparatus

The numbers of gates necessary in an integrated combinatorial logic circuit is reduced by designing the circuit to accept an applied binary word of given length as a plurality of word segments having numbers of bits which add up to the number included in the applied word. A preprocessor responds to the word segments to generate a word characterizing the segments and to apply those words to an arithmetic logic unit designed to add binary words and to generate words having lengths of the applied words.

Circuit for determining the number of ones in a binary signal

Un agencement a amplificateur operationnel monte en reaction (23, 22, 29) est utilise pour produire les impulsions d'horloge ne presentant pas de transitions irregulieres (en 12) a partir d'une source (11) d'impulsions d'horloge presentant des transitions irregulieres. An operational amplifier arrangement mounted in reaction (23, 22, 29) is used to produce the clock pulses having no irregular transitions (12) from a source (11) of clock pulses having irregular transitions. Toute transition irreguliere dans les impulsions d'horloge d'entree se traduit par un changement de la tension moyenne d'une impulsion d'horloge de sortie a la sortie de l'agencement. An improper transition in the input clock pulse results in a change in the average voltage of an output clock pulse at the output of the arrangement. La tension moyenne de l'impulsion d'horloge de sortie est comparee a une tension de reference (25) de maniere a produire un signal de commande qui regle la tension moyenne a la sortie. The average voltage of the output clock pulse is compared with a reference voltage (25) to produce a control signal which controls the average voltage at the output. Des transitions critiques dans les impulsions d'horloge se verifient avec des relations temporelles precises sous la commande du signal de commande. Critical transitions in the clock pulses are verified with precise temporal relationship under control of the control signal.

Robert Harold Krambeck

Papers

B.S.T.J. brief: The buried channel charge coupled device

Charge coupled devices employing nonuniform concentrations of immobile charge along the information channel

Data shifting and rotating apparatus

Circuit for determining the number of ones in a binary signal

Clock pulse-shaping circuit