Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift region partially surrounds the trench. Current flows laterally enabling multiple trench based RESURF DMOS transistors to be formed on a single semiconductor die. The addition of an isolation region to electrically isolate the source from the substrate allows the power transistor to be incorporated into high side driver applications as well as other application mandating electrical isolation between the source and ground.

Top-drain trench based resurf DMOS transistor structure

A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of the substrate. In alternative embodiments, a buffer region of the second conductivity type and having dopant concentration greater than or equal to about the channel region is formed over the top surface of the substrate between the top surface of the substrate and the channel region and lightly doped drain region, wherein the channel region and lightly doped drain regions are doped to a depth to abut the buffer region.

Power LDMOS transistor

In a vertical power field effect transistor, a side surface of a gate electrode is covered with a side oxide film, and a groove is formed in self-alignment with the side oxide film to extend from a surface area of a silicon substrate between a pair of adjacent gate electrodes, to reach a base region. A tungsten film is filled into the groove thus formed, and a source electrode-is formed in contact with the tungsten film within the groove.

Vertical power MOSFET structure having reduced cell area

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Trench-based power semiconductor devices with increased breakdown voltage characteristics

A MOSFET (90,105,170) having a back-side source contact (94,169) and top-side gate (104,166) and drain contacts (98,168) is provided by a structure comprising superposed N⁺ (97,136), N- (96,132),P- (95,128), N⁺ (92,120) regions arranged between top (99,137) and bottom (93,121) surfaces of the semiconductor die (90,105,170). In a preferred implementation, two trenches (100,108) (148,149) are etched from the top surface (99,137) to the P- (95,128), N⁺ (92,120) interface. A buried P- (95,128), N⁺ (92,120) short (110,162) is provided in one trench (108,148) and a gate dielectric (102,160) and gate electrode (104,166) are provided over the sidewall P- (95,128) region exposed in the other trench (100,149). This creates a vertical MOSFET (170) in which the N⁺ substrate (92,120) forms the source region shorted to the P- body region (95,128) in which the channel (106) is created by the gate (104,166). Superior performance is obtained in RF grounded-source circuit applications.

Mosfet with substrate source contact

A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.

Semiconductor device having low source inductance

A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N + , N-,P-, N + regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N + interface. A buried P-, N + short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N + substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

Robert J. Johnsen

Papers

Mosfet with substrate source contact

Semiconductor device having low source inductance

Method for forming a MOSFET with substrate source contact