A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.

Logic module with configurable combinational and sequential blocks

A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

System for distributing clocks using a delay lock loop in a programmable logic circuit

A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected.

Reconfigurable programmable interconnect architecture

A macrocell with product term allocation and adjacent product term stealing is disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms and the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. Because programmable configuration switches can direct individual input product terms to the register logic instead of the OR gate, the register logic can be used even when an adjacent macrocell steals the OR gate.

Registered logic macrocell with product term allocation and adjacent product term stealing

An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

Enhanced field programmable gate array

A programmable sequence generator comprises a combinatorial logic matrix (10,12) and an on-chip timer (24) having count lines (26) coupled as inputs to the logic matrix (10). Combinatorial logic functions may be programmed into the matrix having as variables external inputs (14), a count number represented by the count lines (26) and internal inputs (48) fed back from outputs of he logic matrix (12). In a preferred embodiment, state registers (46) are provided, such that the programmable sequence generator can operate in any one of a plurality of different states. The programmable sequence generator can be configured as a waveform generator (92), a refresh timer (94) or a dynamic memory timing controller (96), among other programmable logic applications.

Programmable sequence generator

A flip-flop circuit has two D type flip-flops. A common system clock drives both flip-flops. A stream of asynchronous data is connected to the data input of the first flip-flop FF1. The output of FF1 is connected to the data input of the second flip-flop FF2. The timing characteristics of FF1 and FF2 are chosen so that the time from the clock pulse to the high logic output of FF1 plus the set up time of FF2 is less than the minimum propagation delay time of FF2.

Metastable resistant flip-flop

A logic output macrocell (30) is programmable to select between a registered output (38a-n) or a nonregistered output (42a-n). The selection between the two outputs can be either reversible through coupling to a selecting output (58) of a combinatorial logic matrix (12) or it can be permanently programmed with the aid of an architectural fuse (52a-n).

Robert K. Breuninger

Papers

Programmable sequence generator

Metastable resistant flip-flop

Logic output macrocell