Patent
Metastable resistant flip-flop
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TLDR
In this paper, a flip-flop circuit has two D type flipflops, and a common system clock drives both flip flops, each of which is connected to the data input of the first flip flop FF1.Abstract:
A flip-flop circuit has two D type flip-flops. A common system clock drives both flip-flops. A stream of asynchronous data is connected to the data input of the first flip-flop FF1. The output of FF1 is connected to the data input of the second flip-flop FF2. The timing characteristics of FF1 and FF2 are chosen so that the time from the clock pulse to the high logic output of FF1 plus the set up time of FF2 is less than the minimum propagation delay time of FF2.read more
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References
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Patent
Synchronizing circuit including two flip-flops and circuit means to protect a synchronized signal from an unstable state of the flip-flops
TL;DR: In this article, the flip-flops are used to synchronize a data signal to a clock pulse and a temporizing circuit is used to protect against the flips synchronizing in an unstable state due to the critical period of sampling edge of the clock pulse.
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Asynchronous signal synchronizing circuit
TL;DR: An asynchronous signal synchronizing circuit for sampling and external asynchronous signal in a quarter of the period of a clock can be found in this article, where a first latch circuit latches asynchronous input signal in accordance with a first clock, and a second latch circuit latchches the output of the first circuit having a phase shift 180° out of phase with the first clock.
Patent
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TL;DR: In this paper, a synchronizing circuit using a switchable bistable element for synchronizing an asymmetric signal with the clock of a data processing system is described. But the synchronizing element does not support the maintenance of a balanced or metastable state.
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Method and apparatus for the error-free synchronization of asynchronous pulses
TL;DR: In this article, an error-free synchronization of asynchronous pulses through logical interconnection of the asynchronous pulses with clock pulses of constant frequency by means of a flip-flop is presented.