The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

Method and apparatus for significantly improving the reliability of multilevel (MLT) memory architecture. Before writing to MLT architecture, each MLT word is encoded into a coded bit stream in such a way that the resultant coded data contains the original word plus additional digits which are a function of the content of memory. During the reading of the memory, the stored data is decoded, and takes advantage of redundancy to correct and eliminate errors introduced during read and write operations of the MLT architecture. The invention is useful for systems such as general-purpose computers (PCs, workstations, etc.), telecommunications devices (telephones—wired and wireless, switches, hubs, routers, etc.), audio and visual devices (recording and playback, editing, format switching, compression, etc.), vehicles (automobiles, aircraft, trains, boats, satellites, spacecraft, etc.). Systems and subsystems may be incorporated on a single integrated circuit (IC) die having MLT RAM or enhanced MLT memory. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

Method and apparatus for significantly improving the reliability of multilevel memory architecture

A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code when stored in the flash-memory chips. A DRAM cache stores the pages of data as enlarged pages with the overhead bytes, even though the enlarged pages are not aligned to a power of 2. When an enlarged page is read out of a flash-memory chip, its ECC code is immediately checked and the ECC code in the overhead bytes is replaced with a syndrome code and stored in the DRAM cache. A local processor for the flash-memory system then reads the syndrome code in the overhead bytes and repairs any error using repair information in the syndrome. The overhead bytes are stripped off when pages are transferred from the DRAM cache to a host. The host can be notified early by an intermediate interrupt after a programmable number of pages have been read. This improves performance since the host does not have to wait for an entire block of pages to be read.

Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations

Quaternary CAM cells are provided that include one or more compare circuits that each has a minimal number of pull-down transistors coupled between the match line and ground potential. For some embodiments, the compare circuit includes two parallel paths between the match line and ground potential, with each parallel path consisting of a single pull-down transistor having a gate selectively coupled to the stored data value in response to a comparand value.

Fast quaternary content addressable memory cell

Methods and apparatus for using different error correction code algorithms to encode and to decode contents of blocks within a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing data within a non-volatile memory includes identifying a first block into which the data is to be stored, and obtaining an indicator associated with the first block. A determination may then be made regarding whether the indicator indicates that the data is to be encoded using a first algorithm. The data is encoded using the first algorithm when it is determined that the data is to be encoded using the first algorithm, after which point the data encoded using the first algorithm is written into the first block.

Hybrid implementation for error correction codes within a non-volatile memory system

In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

In a memory system, which includes a dynamic random access memory (DRAM) that has to be precharged before the contents thereof can be selectively read out into a static register, there is provided means for reading the memory contents of the memory cells of a part or the whole of a row of memory cells of the DRAM into the static register while concurrently precharging the DRAM for a subsequent read-out command. This reduces the overall cycle time of the memory array since read-out of the static register can occur during precharge.

Early row address strobe (RAS) precharge

973,118. Sensing record cards. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 4, 1962 [April 14, 1961], No. 12897/62. Heading G4M. A perforated record card is sensed columnby-column by energizing neon lamps L1-L80 in sequence, photoconductive strips PC1-PC12, one for each row of the card, providing output signals representing the recorded data and also controlling the energization of lamps L1-L80 in such a way that if any column of the card is not perforated, the next lamp in the sequence is energized after a shorter time interval than the normal decay period of strips PC1-PC12 or the normal extinction period of lamps L1-L80. Each lamp L1-L80 is provided with a lucite light guide 46 and is pulsed on by the corresponding monostable circuit D1-D80 triggered by the associated stage of a ring counter 9. A start pulse at terminal 42 pulses lamp L1, and if one or more holes are present in the first column of the card an output is obtained from OR gate 35 to trigger commutator 16 which then scans the strips PC1-PC12 to produce a differentially-timed pulse (or pulses) on lead 18. The output of OR gate 35 also inhibits gate 38 to prevent the start pulse, which has been delayed by network 32, from stepping on the ring counter 9 through OR gate 31. At the completion of a scan, commutator 16 pulses lead 17, and after a suitable delay introduced by network 34, the next lamp L2 is pulsed on. If there are no holes in a column, no output is obtained from OR gate 35, commutator 16 is not triggered and gate 38 is not inhibited, so that the pulse which initiated energization of the corresponding lamp, after passing through network 32, is recirculated and causes the next lamp to be energized. The output of strips PC1-PC12 may be taken directly from amplifiers 14, in which case commutator 16 is omitted, line 15 is connected to line 17 and delay 34 suitably adjusted to account for the decay time of the strips of the extinction time of the lamps.

Electro-optical card reader

A system for refreshing and scrubbing data contained in a DRAM during each and every refresh cycle is disclosed. Briefly stated, a standard refresh address counter has its bit length extended with the result that the-extended bits are used as a column address which when used with a conventional row address during a refresh cycle are used to select memory locations which are refreshed and scrubbed while adjacent memory locations are refreshed only. The read/write enable lead is deactivated during the refresh cycle. The DRAM is in effect forced into performing a read operation with the result that data is refreshed and scrubbed contemporaneously as normally done during a read or write.

Overlapped data scrubbing with data refreshing

A monitoring arrangement for enabling communication between a data processing system and remote users thereof in which there are included means for enabling communication between an operator and the system to permit examination of the data being sent by the system, means for enabling communication between remote users and the system to permit examination of the data being sent by the users to the system and means for alternately consecutively enabling the system information and the user information to be observed to effectively achieve bidirectional intercommunication between the system and the users. The arrangement is capable of operating in both the audio and digital modes.

Robert Martin Blake

Papers

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

Early row address strobe (RAS) precharge

Electro-optical card reader

Overlapped data scrubbing with data refreshing

Communications monitor for data processing system