A universal remotely controlled test interface test unit is adapted to be connected through plug connections to an on-site computing system having one or more central processing units and associated peripheral equipment. The test interface unit is provided with a limited function keyboard control for initiating tests and a transceiver for communicating with a data processing unit at a remote location which supplies format and control signals for use by the test interface unit and data signals to be communicated to the on-site computing system. The data signals received by the test interface unit are first entered into a buffer register to provide parallel outputs. The format control signals activate logic gating signals to cause the data signals in the buffer register to be arranged in a control register in a format which is compatible with the equipment to be tested. The control register is arranged to operate any part of the central processing system under test and any of its intended modes of operation and to initiate readout of information from any part of the computing system through the transceiver for processing and examination by the remotely located data processing unit.

Remote controlled test interface unit

A test automation system (Fig. 1) comprises storage and process components connected by file interfaces. BPLAN (103) creates and stores test descriptions in test information database (102). Tests are stored in test storage hierarchy (100). BSYNC (104) completes test descriptions in database (102) form contents of hierarchy (100). BQUERY (105) examines descriptions and selects tests for execution. TESTLOCS file (106) identifies selected tests. BQUERY (105) uses BBC (118) to communicate requests for tests and test descriptions to other systems. BBCMON (120) causes BQUERY (105) to satisfy requests and uses BBC (118) to communicate responses to requesting systems. BDLOAD (107) gathers tests identified by file (106) from hierarchy (100) into file (117) for downloading from host (10) to target (11) processor. BRUN (109) executes downloaded tests, collects test results in files (110-112), and reports result summaries. BULOAD (113) assembles files (110-112) into file (114) for uploading to processor (10). BSTORE (115) stores uploaded results in results database (116). BQUERY (105) examines test results collected in database (116).

Test automation system

A method and apparatus for generating a digital image representation of a printed circuit board. The board has a substrate of insulating material. A pattern of metallic conductors is disposed on a surface of the insulating material. A beam of light energy scans this surface in a predetermined pattern. The beam has an energy level high enough to induce a detectable fluorescence in the surface of the insulating material. This fluorescence is detected and a binary signal is generated to indicate the presence or absence of fluorescence as the beam scans the surface. The binary signal is synchronized with the scanning of the beam such that a binary image representation of the board's surface is provided.

Method of inspecting circuit boards and apparatus therefor

A system for automatically testing a plurality of memory arrays on selected memory array testers includes an interactive data entry device for entering array test specifications including characterizing information, DC testing parameters, AC testing parameters and AC test pattern choices for the array. The test specifications are entered in a format which is independent of a particular tester's characteristics. A universal language generator generates a tester independent universal language instruction sequence for carrying out the prescribed tests based upon the entered test specifications. Associated with each tester is a universal language translator which translates the tester independent universal language instruction sequence into an instruction sequence which is particular to the associated tester. The tester dependent instruction sequence may be loaded into the associated tester to produce the test signals for testing the memory array.

Automatically testing a plurality of memory arrays on selected memory array testers

A method and apparatus for regulating a measurement system. The apparatus includes a coordinator that transmits instruction signals based upon a program stored in a memory to an instrument through a communication bus. The instrument is also coupled to a device under test. A real-time synchronized clock and a data buffer are placed on each instrument that performs a measurement, provides a stimulus, controls a device, manages data, or performs a test. Signals passing between the device under test and the instrument are processed by function circuitry. After the measurement is made and a parameter or an output signal from the device under test is collected by the instrument, the real-time clock supplies a reference time signal which is associated with each parameter or group of data derived from the device under test. The data buffer stores each group of data with its associated reference time signal until the coordinator calls for the instrument to dispatch the results of the measurement or stimulus back along the communication bus in the form of an instrument output signal. If the instrument provides a stimulus to the device under test, the stimulus appears as an input signal in accordance with the instruction signal which has been stored in data buffer. The stimulus is triggered by a timing signal from the real-time clock.

Measurement system control using real-time clocks and data buffers

A testing system wherein a digital computer controls programmable testing devices which supply signals to, and receive signals from, a unit under test. Buffer interface equipment is connected to three input/output channels of the computer and includes a plurality of storage registers connected to the various programmable test devices. Information to be supplied to the test devices is received via one input/output channel and placed into storage. Test results are also placed into storage and transmitted back to the computer for analysis via a second channel. The third channel contains address information for selecting which storage registers receive or transmit the digital signals.

Universal buffer interface for computer controlled test systems

A system for evaluating members or a family of similar devices by comparing images of a model device to the image of the member to be evaluated is disclosed. An image of the model device is first produced and stored in a memory. An image of the member to be evaluated is produced as the stored image of the model device is simultaneously reproduced. The images of the model and the member being evaluated are compared to generate a comparison signal related to the differences therebetween. The comparison signal is sampled at a predetermined rate, to produce a digital signal indicating sample points where the comparison signal exceeds a predetermined value. Statistical techniques are used to analyze the digital signal to determine which portions of this signal correspond to significant differences between the images of the model device and the member being evaluated. The portions of the digital signals corresponding to significant differences between images of the model and device being evaluated are combined with the image of the device being evaluated to produce a multicolor composite image. In the composite image areas of the image of the device being evaluated which are significantly different from the image of the model device are displayed in red with the remainder of the composite image being green.

Robert Martinez

Papers

Universal buffer interface for computer controlled test systems

Sampled differential analyzer