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Showing papers by "Robert W. Brodersen published in 2012"

Book Chapter•DOI•
MHz-rate Multi-Antenna Decoders: Flexible Sphere Decoder Chip Examples

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Dejan Markovic1, Robert W. Brodersen2, Chia-Hsiang Yang3•
University of California, Los Angeles1, University of California, Berkeley2, National Chiao Tung University3
01 Jan 2012
TL;DR: This chapter discusses design techniques for dealing with design flexibility, in addition to complexity that was discussed in the previous chapter, with emphasis on flexible FFT that operates over many signal bands.
Abstract: This chapter discusses design techniques for dealing with design flexibility, in addition to complexity that was discussed in the previous chapter. Design techniques for managing adjustable number or antennas, modulations, number of sub-carriers and search algorithms will be presented. Multi-core architecture, based on scalable processing element will be described. At the end, flexibility for multi-band operation will be discussed, with emphasis on flexible FFT that operates over many signal bands. Area and energy cost of the added flexibility will be analyzed.
Book Chapter•DOI•
Time-Frequency Analysis: FFT and Wavelets

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Dejan Markovic1, Robert W. Brodersen2, Rashmi Nanda3, Vaibhav Karkare3•
University of California, Los Angeles1, University of California, Berkeley2, University of California3
01 Jan 2012
TL;DR: This chapter uses the FFT and the wavelet transform as examples for this chapter and discusses the methods for time frequency analysis and the DSP architectures for implementing these methods.
Abstract: In this chapter we will discuss the methods for time frequency analysis and the DSP architectures for implementing these methods. In particular, we will use the FFT and the wavelet transform as our examples for this chapter. The well-known Fast Fourier Transform (FFT) is applicable to the frequency analysis of stationary signals. Wavelets provide a flexible time-frequency grid to analyze signals whose spectral content changes over time.
Book Chapter•DOI•
MHz-rate Multi-Antenna Decoders: Dedicated SVD Chip Example

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Dejan Markovic1, Robert W. Brodersen2, Borivoje Nikolic3, Chia-Hsiang Yang4•
University of California, Los Angeles1, University of California, Berkeley2, University of California3, National Chiao Tung University4
01 Jan 2012
TL;DR: This chapter will demonstrate hardware realization of multidimensional signal processing by adaptive algorithm for singular value decomposition, with emphasis on managing design complexity and minimizing power and area for complex signal processing algorithms.
Abstract: This chapter will demonstrate hardware realization of multidimensional signal processing. The emphasis is on managing design complexity and minimizing power and area for complex signal processing algorithms. As an example, adaptive algorithm for singular value decomposition will be used. Power and area efficiency derived from this example will also be used as a reference for flexibility considerations in Chap. 15.