Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

An improved conductivity vertical channel semiconductor device includes an insulated gate electrode disposed adjacent a substantial portion of the voltage supporting region. In response to an appropriate bias, the control electrode couples to the electric field originating on charges within the voltage supporting region to reorient the electric field associated with those charges toward the gate electrode and transverse to the direction of current flow through the device. Improved control of the electric field within the voltage supporting region allows the doping concentration, and hence the conductivity of the channel, to be improved without a concomitant decrease in breakdown voltage. Accordingly, the channel width and cell repeat distance of the improved device can be reduced, allowing for an improved current density to be established throughout an overall device cell structure. The charge control region of the voltage supporting layer exhibits an aspect ratio of 0.5.

Semiconductor devices exhibiting minimum on-resistance

A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. The via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies with vias can be stacked on top of each other or surface mounted to printed circuit boards or other substrate.

Method of bonding wafers having vias including conductive material

A trenched device, such as a DMOS transistor, provides for higher breakdown voltages than possible using trenched devices of the prior art. The trench extends only into the epitaxial layer, thereby minimizing breakdown problems associated with prior art trench devices in which the trench extends into the more highly doped substrate. However, in order to achieve higher breakdown voltages, the dopant concentration is increased in that portion of the epitaxial layer surrounding the bottom of the trench. Thus, a novel trenched device is taught which achieves higher breakdown voltages by causing the trench to be surrounded by relatively highly doped material, while not requiring the trench to extend into the more highly doped substrate itself.

Method for increasing the performance of trenched devices and the resulting structure

A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. the via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies 335a, 335b, 335c with conductive vias are stacked on top of each other. Other dies 341, 343 are connected together with an optical coupling die 342.

System for interconnecting stacked integrated circuits

Bidirectional power FET structure is disclosed with high OFF state voltage blocking capability. A shielding electrode is insulated between first and second gate electrodes in a notch between laterally spaced source regions and channel regions joined by a common drift region around the bottom of the notch. The shielding electrode is ohmically connected to the substrate containing the common drift region to be at the same potential level thereof and within a single junction drop of a respective main electrode across the junction between the respective channel containing region and drift region. The steering diode function for referencing the shielding electrode is performed by junctions already present in the integrated structure, eliminating the need for discrete dedicated steering diodes. The shielding electrode prevents the electric field gradient toward the gate electrode on one side of the notch from inducing depletion in the drift region along the opposite side of the notch. This prevents unwanted inducement of conduction channels in the drift region during the OFF state of the FET.

Bidirectional power FET with substrate-referenced shield

Lateral FET structure is disclosed for bidirectional power switching, including AC application. A notch extends downwardly from a top major surface to separate left and right source regions and left and right channel regions, and direct the drift region current path between the channels around the bottom of the notch. Gate electrode means in the notch proximate the channels controls bidirectional conduction.

Lateral bidirectional notch FET with extended gate insulator

Various circuits and combinations of radiant energy responsive transducer means such as photovoltaic diodes connected to the gate of a depletion mode FET whose source and drain are connected to the gate and cathode of a thyristor, are disclosed to provide a semiconductor switch which is triggered into conduction solely by a small amount of radiant energy, without the need for a second triggering energy source, and which also affords immunity to unwanted dv/dt and temperature induced turn-on. Various modes of operation are disclosed, including the thyristor self-triggering into conduction, and/or being of the light-activated type itself and being directly triggered by impinging light, and/or being triggered by the light-responsive diode bias, and/or being triggered by a small bias supplied from a second set of photovoltaic diodes connected to the thyristor gate. Other combinations are disclosed providing zero-cross firing.

Radiant energy activated semiconductor switch

Germanium semiconductor temperature switches are described which are capable of intrinsically switching between high and low resistance states within a temperature range up to 55°C, and are adapted for operating at voltages up to 400 volts. These temperature switches are disclosed in various configurations. Basic circuits for adjusting the temperatures at which such switches switch within a range are disclosed. Preferred methods of making the same are also disclosed.

Semiconductor temperature switches

A monolithic semiconductor device is disclosed comprising a power switching thyristor and a temperature sensitive thyristor integrated on a common substrate. In preferred form, the temperature sensitive thyristor is electrically connected between the gate terminal and one of the main terminals of the power switching thyristor, and is thermally actuatable to intrinsically switch from a high to a low resistance state above a predetermined temperature of the power switching thyristor sensed through the common substrate, whereby to shunt gate current and automatically inhibit turn-on of the power switching thyristor to prevent overheating thereof. Depending on circuit variations, the power switching thyristor may be rendered conductive above or below a predetermined temperature, or within a defined temperature range. Normally off and normally on devices are disclosed.

Robert W. Lade

Papers

Bidirectional power FET with substrate-referenced shield

Lateral bidirectional notch FET with extended gate insulator

Radiant energy activated semiconductor switch

Semiconductor temperature switches

Integrated thermally sensitive power switching semiconductor device, including a thermally self-protected version