A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Method and system for context-specific mask inspection

Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table. The bias table can include both rule-based and model-based actions, and can also include single-edge shapes for completeness. The scanning of the IC layout can be performed in order of increasing or decreasing complexity, or can be specified by the user. The appropriate layout processing actions are applied to matching portions of the IC layout to form the corrected photomask layout. This process can be sequential or batch mode. Shape and action conflicts can be resolved by marking identified/modified elements or by designing rules for orderly resolution of any inconsistencies or overlaps.

General purpose shape-based layout processing scheme for IC layout modifications

A process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, non-homogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etching chamber 30. In the etching step, process gas comprising etchant gas is used to etch a substrate 25 in the etching chamber 30 thereby depositing etch residue inside the chamber 30. Cleaning gas is added to the process gas for a sufficient time and in a volumetric flow ratio that is sufficiently high, to react with and remove substantially all the etch residue deposited by the process gas. The present method advantageously cleans the etch residue in the chamber 30, during the etching process, and without use of separate cleaning, conditioning, and seasoning process steps.

Self-cleaning etch process

A chip package includes: a substrate; a signal pad and a ground pad disposed on the substrate; a first and a second conducting layers disposed on the substrate and electrically connected to the signal pad and the ground pad, respectively, wherein the first and the second conducting layers extend from an upper surface of the substrate towards a lower surface of the substrate along a first and a second side surfaces of the substrate, respectively, and the first and the second conducting layers protrude from the lower surface; and a protection layer disposed on the substrate, wherein the protection layer completely covers the entire portion of the first conducting layer located on the first side surface of the substrate, and the entire portion of the second conducting layer located on the second side surface of the substrate is not covered by the protection layer.

Chip package and method for forming the same

Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Dissection of printed edges from a fabrication layout for correcting proximity effects

A method of forming a hybrid mask for optically transferring a lithographic pattern corresponding to an integrated circuit from the mask onto a semiconductor substrate by use of an optical exposure tool. The method includes the steps of forming at least one non-critical feature on the mask utilizing one of a low-transmission phase-shift mask (pattern) and a non-phase shifting mask (pattern), and forming at least one critical feature on the mask utilizing a high-transmission phase-shift mask (pattern).

Hybrid phase-shift mask

A method for forming an alignment mark during semiconductor device manufacturing. A first area and a second area are provided on the semiconductor substrate wherein the second area is adjacent to the first area. An alignment mark is formed in the first area. A first layer is formed over the first area and the second area wherein the alignment mark is replicated in the first layer. The first layer is then removed from the second area and left over the first area. A globally planarized second layer, is formed over the first area and the second area. The second layer is then removed from the first area and is left over the second area.

Method of fabrication an inverse open frame alignment mark

A method for forming an alignment mark during semiconductor device manufacturing. A first alignment mark having a first step height is formed in a semiconductor substrate. An interlayer dielectric is formed over the alignment mark and planarized to a first thickness. During contact/via etch an opening is formed through the first dielectric layer away from the first alignment mark. The opening is then filled with a material until the material in the bottom of the opening has a thickness less than thickness of the planarized dielectric layer.

Chemical-mechanical alignment mark and method of fabrication

A method for making a mask for optically transferring a lithographic pattern corresponding to an integrated circuit from the mask onto a semiconductor substrate by use of an optical exposure tool. The method includes the steps of de-composing the existing mask patterns into arrays of 'imaging elements'. The imaging elements are π-phase shifted and are separated by non-phase shifting and sub-resolution elements referred to as anti-scattering bars (ASBs). In essence, the ASBs are utilized to de-compose the larger-than-minimum-width mask features to form 'halftone-like' imaging patterns. The placement of the ASBs and the width thereof are such that none of the π-phase shifting elements are individually resolvable, but together they form patterns substantially similar to the intended mask features.

Method of patterning sub-0.25 lambda line features with high transmission, "attenuated" phase shift masks

The present invention provides a method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug of an associated contact or via hole. In accordance with the preferred embodiment of the present invention, a silicon substrate is provided having at least one device region formed at the surface of the substrate. An insulating layer is deposited over the substrate having at least one contact hole formed through the insulating layer to expose the device region. A first blanket layer of titanium is deposited as a tungsten adhesion layer over the insulating layer and the exposed device region within the contact hole. A second blanket layer of titanium-tungsten or titanium-nitride is then deposited as a tungsten barrier layer over the adhesion layer. Subsequently, a blanket contact plug layer comprising tungsten is deposited over the barrier layer by chemical vapor deposition. Both the contact plug layer and the barrier layer are then removed from the surface of the adhesion layer everywhere except within the contact hole by a selective etch back process wherein a selectivity between tungsten and titanium of at least 5:1 is achieved. Next, the exposed portions of the adhesion layer are patterned with a mask and etched to remove those portions of the adhesion layer not covered by the mask, thus converting the adhesion layer into a thin film interconnect or landing pad underlying the contact plug of the associated contact hole.

Roger F. Caldwell

Papers

Hybrid phase-shift mask

Method of fabrication an inverse open frame alignment mark

Chemical-mechanical alignment mark and method of fabrication

Method of patterning sub-0.25 lambda line features with high transmission, "attenuated" phase shift masks

Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole