Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

Delay locked loop circuitry for clock delay adjustment

A serial intelligent cell (SIC) and a connection topology for local area networks using Electrically-conducting media. A local area network can be configured from a plurality of SIC's interconnected so that all communications between two adjacent SIC's is both point-to-point and bidirectional. Each SIC can be connected to one or more other SIC's to allow redundant communication paths. Communications in different areas of a SIC network are independent of one another, so that, unlike current bus topology and star topology, there is no fundamental limit on the size or extent of a SIC network. Each SIC can optionally be connected to one or more data terminals, computers, telephones, sensors, actuators, etc., to facilitate interconnectivity among such devices. Networks according to the present invention can be configured for a variety of applications, including a local telephone system, remote computer bus extender, multiplexers, PABX/PBX functionality, security systems, and local broadcasting services. The network can use dedicated wiring, as well as existing wiring as the in-house telephone or electrical wiring.

Local area network of serial intelligent cells

A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

Disclosed is an acoustic resonator that includes a substrate, a first electrode, a layer of piezoelectric material, a second electrode, and an alternating frame region. The first electrode is adjacent the substrate, and the first electrode has an outer perimeter. The piezoelectric layer is adjacent the first electrode. The second electrode is adjacent the piezoelectric layer and the second electrode has an outer perimeter. The alternating frame region is on one of the first and second electrodes.

Acoustic resonator performance enhancement using alternating frame structure

An automatic configuration system maps a device address of each node coupled to a bus structure to a network protocol address corresponding to the physical location of the node. A configuration database is built which includes the network protocol address of each node and its corresponding device address. A wiring database, including each device position within the network, is maintained within a network server. Preferably, the network is an IEEE 1394 serial bus network. A topology map, including the device addresses of the nodes within the network and their relationship to each other, is generated during a self-ID sequence and is maintained by the network server. This information is then compared to the wiring database by the network server in order to build a restored topology map including the corresponding device address for each device at each position. A DHCP database is then generated which includes each device address and its corresponding network protocol address. The network protocol address corresponds to the position of the respective device. Using the DHCP database, the network protocol address is maintained for the devices at each position, in order to monitor the positions of the devices and communications from the devices.

Automatic configuration system for mapping node addresses within a bus structure to their physical location

The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal differentiator for receiving an NRZ data signal and outputting a differentiated signal. A driver comprising a tri-state gate has as a first input the data signal and as a second input the differentiated signal for enabling the tri-state gate when the differentiated signal is high. A bias voltage is applied to an output of the tri-state gate to derive as output a transmission signal for transmission via the bus accross the interface between the two devices. In this way, the transmission signal output from the first device comprises an intermediate transmission signal corresponding to the bias voltage when the tri-state gate is disabled, a hight transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is high, and a low transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is low. A Schmidt trigger is provided as a receiver in the second device for receiving as input the transmission signal and outputting a reconstituted data signal corresponding to the synchronized data signal.

Method and apparatus for transmitting nrz data signals across an isolation barrier disposed in an interface between adjacent devices on a bus

A node for a communication system that has a plurality of nodes, each of which may be coupled to a local host. The nodes are coupled between themselves in a tree topology by a plurality of point-to-point links. The interconnected nodes provide a first bus configuration for arbitration like a single bus. Following arbitration, the interconnected nodes provide a second configuration for high speed unidirectional data transfer without the bandwidth limitations of a single bus. Each node includes an arbiter, a data bus, a plurality of ports, a first multiplexer to select either the arbiter or the data bus, and a second multiplexer to select either the arbiter or the data bus. The data bus includes a transmit bus and a receive bus that are coupled with a repeater circuit that can resynchronize the data. During arbitration, the multiplexers select the arbiter to provide the function of a single bus for all the nodes. During data transfer, the multiplexers are configured for transmission of data. Furthermore, a node can function as a repeater and resynchronizer even if it is not connected to a local host or if the local host is turned off or otherwise nonoperational.

A communication node with a first bus configuration for arbitration and a second bus configuration for data transfer

A mechanism and method for efficiently communicating information regarding particular communication rate ("speed signal") between two or more communication stations (of a communication network). The transmitter operates on the IEEE P1394 High Performance Serial Bus to supply both differential and common mode signaling required by the IEEE standard for exemplary data transfer rates of 100 and 200 Mbit transmission. The present invention includes a transmission circuit that may operate in a differential signal mode and simultaneously in a common mode signal mode both utilizing a twisted pair cable. Data may be transmitted on the twisted pair at small differential signals. Information regarding the signal speed between two coupled units may be simultaneously transmitted using variations in the common mode voltage over the twisted pair. Communication may be initiated at a slower communication rate and then upgraded as appropriate for the two units. The present invention allows an efficient single circuit mechanism for communication units to transmit differential data and also to signal the use of a high speed communication rate with a common mode voltage. The present invention is especially useful within networks having units of varying versions and signal transfer rates.

Circuit and method for twisted pair current source driver

A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port (30) in the node includes a bus driver (150) that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus (40). A terminator circuit (50) is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus (42), which is coupled to the plurality of ports for transmission. A biasing circuit (80) for the bus drivers allows operation at low voltages, and furthermore insures that the zero crossing of the differential input signals is equivalent to the zero crossing of the differential voltage signal on the second differential bus.

High-speed dominant mode bus for differential signals

In a driver circuit for a twisted pair cable, a compensator for preventing appreciable common mode current flow into or out of the twisted pair cable in response to the device receiving a wide range of common mode voltage bias levels. A wide range of external bias voltages may be received as a result of variations in the ground node voltages of two coupled devices. The compensator circuit utilizes a feed back loop and monitors the bias voltage received on the twisted pair cable. As the magnitude of the common mode current increases due to external bias voltage variation from a reference bias voltage, the current flow of p-channel transistors, coupled in an arrangement of the present invention, is increased (or decreased, as necessary) so that reduced common mode current flows onto the twisted pair cable. The present invention reduces appreciable common mode current flow through the twisted pair cable from the driver that are due to variations in the external bias voltage between communication devices. The present invention provides high common mode output impedance for the driver circuit by altering the effective common mode common mode early voltage characteristics of the driver circuit while utilizing shorter channel length transistors for high speed communication capacity. The present invention also offers reduced current supply capacity of the common mode bias voltage source. The present invention operates ideally within driver circuits compatible with the IEEE P1394 communication standard.

Roger Van Brunt

Papers

Method and apparatus for transmitting nrz data signals across an isolation barrier disposed in an interface between adjacent devices on a bus

A communication node with a first bus configuration for arbitration and a second bus configuration for data transfer

Circuit and method for twisted pair current source driver

High-speed dominant mode bus for differential signals

Common mode early voltage compensation subcircuit for current driver