Showing papers by "Romano Fantacci published in 1992"
TL;DR: Performance of the proposed stop-and-wait ARQ scheme is derived in terms of throughput efficiency, mean waiting time and buffer occupancy and it is shown that the scheme provides better performance with the respect to previously proposed schemes.
Abstract: The author presents an efficient stop-and-wait ARQ (automatic repeat request) technique for error control in data communication systems. Performance of the proposed stop-and-wait ARQ scheme is derived in terms of throughput efficiency, mean waiting time and buffer occupancy. It is shown that the scheme provides better performance with the respect to previously proposed schemes. In particular it is attractive for error control in data communication systems under high error rate conditions. >
9 citations
TL;DR: The test results confirm the MCD feasibility, and further improvements are expected from a semicustom implementation, as well as the requirement that new-generation payloads could serve the stations already active in the INTELSAT Business System.
Abstract: Frequency-division multiple access (FDMA) and single channel per carrier (SCPC) in the uplink and time-division multiplexing (TDM) in the downlink are employed in the system described. To interface FDMA in the uplink and TDM in the downlink, multicarrier demodulation (MCD) is required onboard the satellite. The operation of the onboard MCD is the separation of each individual channel and subsequent demodulation. The results, which concern onboard frequency demultiplexing and demodulation for low-bit-rate carriers, are constrained by the requirement that new-generation payloads could serve the stations already active in the INTELSAT Business System. A digital hardware design that implements an MCD that can process three channels at 4.4 Mb/s or 12 channels at 1.1. Mb/s is described. The test results confirm the MCD feasibility, and further improvements are expected from a semicustom implementation. >
6 citations
06 Dec 1992
TL;DR: An efficient high-speed packet switching in which each packet arrived at an input is stored in one of N possible queues, one for each possible output link, is discussed and the proposed multiple input queueing approach outperforms the outputQueueing approach without requiring a speedup in the switching operations.
Abstract: An efficient high-speed packet switching in which each packet arrived at an input is stored in one of N possible queues, one for each possible output link, is discussed. An implementation architecture which makes it possible for the N separate queues to share the same input buffer is considered. An important result is that the proposed multiple input queueing approach outperforms the output queueing approach without requiring a speedup in the switching operations. >
5 citations
16 Mar 1992
TL;DR: An important result shown in the paper is that the proposed multiple input queueing approach outpetfom the outputQueueing approach without requiring a speed-up in the switching operations.
Abstract: This paper deals with an eflcient highspeed packet swiitching in which each packet arrived at an inpuit is stored in one of Npossible queues, one for tmh possible output link. An implementation architecture which permits to share by the N separate queues the same input bufer is considered and studied. An important result shown in the paper is that the proposed multiple input queueing approach outpetfom the output queueing approach without requiring a speed-up in the switching operations.