Semiconductor science and technology (S T) is a very active branch in the field of natural science, and is also a typical example embodying the development of advanced S T. The Nobel prize for physics is a prize of the highest honour in the world, and there are certain relationships between this award and semiconductor S T. We explore and analyze these inherent relationships which have practical importance for our understanding of the development of semiconductor S T and for predicting its future.

Semiconductor science and technology, and Nobel physics prizes

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-μm CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 μVrms and 163 μVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible baseband analog circuits for software-defined radio front-ends

The Department of Transport in the United Kingdom recorded 25,080 motor vehicle fatalities in 2019. This situation stresses the need for an intelligent transport system (ITS) that improves road safety and security by avoiding human errors with the use of autonomous vehicles (AVs). Therefore, this survey discusses the current development of two main components of an ITS: (1) gathering of AVs surrounding data using sensors; and (2) enabling vehicular communication technologies. First, the paper discusses various sensors and their role in AVs. Then, various communication technologies for AVs to facilitate vehicle to everything (V2X) communication are discussed. Based on the transmission range, these technologies are grouped into three main categories: long-range, medium-range and short-range. The short-range group presents the development of Bluetooth, ZigBee and ultra-wide band communication for AVs. The medium-range examines the properties of dedicated short-range communications (DSRC). Finally, the long-range group presents the cellular-vehicle to everything (C-V2X) and 5G-new radio (5G-NR). An important characteristic which differentiates each category and its suitable application is latency. This research presents a comprehensive study of AV technologies and identifies the main advantages, disadvantages, and challenges.

A Survey of Autonomous Vehicles: Enabling Communication Technologies and Challenges.

The intelligent transport system (ITS) has become one of the most globally researched topics with a lot of investment and development resources being dedicated into it due to its foreseen impact on the economic growth of the transport sector. Currently there are two main vehicle-to-everything (V2X) technologies, whose primary application is focused on ITS, backed up by the key players of various automotive, telecommunication and transport industries: dedicated short-range communications (DSRC) and cellular vehicle-to-everything (C-V2X), respectively based on IEEE 802.11p and 3GPP LTE/5G NR. While DSRC already has deployments, C-V2X is expected to see larger scale trails and deployments in 2020. In this work, the authors provide insight and review into two main V2X technologies, DSRC and C-V2X, their core parameters, shortcomings and limitations, and explore the need for integration of IoT-based technologies into modern ITS solutions. A comprehensive overview and analysis of currently commercially available V2X products, their sub-blocks and features is provided.

Review of V2X–IoT Standards and Frameworks for ITS Applications

This study reviews the current situation regarding design protection in the microelectronics industry. Over the past 10 years, the designers of integrated circuits (IC) and intellectual properties (IP) have faced increasing threats including counterfeiting, reverse-engineering and theft. This is now a critical issue for the microelectronics industry, mainly for fabless designers and IP designers. Coupled with increasing pressure to decrease the cost and increase the performance of ICs, the design of a secure, efficient, lightweight protection scheme for design data is a serious challenge for the hardware security community. However, several published works propose different ways to protect design data including functional locking, hardware obfuscation and IC/IP identification. This study presents a survey of academic research on the protection of design data. It concludes with the need to design an efficient protection scheme based on several properties.

/pdf/survey-of-hardware-protection-of-design-data-for-integrated-20kr0nr05d.pdf

Survey of hardware protection of design data for integrated circuits and intellectual properties

New methods for automated visual recognition of metal interconnect technological layers of integrated circuits are presented. Image processing and analysis algorithms are used in these methods to extract interconnect structure locations and dimensions. Recognized structure data is used to recreate initial photolithographic mask data suitable for further analysis. Proposed methods were experimentaly tested and their precision was calculated from test results. To perform experimental testing, custom software was developed as a framework for this and future research. Methods proposed here are initial part of collection of methods suitable for complete chip topological structure extraction, including all layers. Ill. 4, bibl. 13 (in English; summaries in English, Russian and Lithuanian).

/pdf/reverse-engineering-of-cmos-integrated-circuits-5abu94gefo.pdf

Reverse engineering of CMOS integrated circuits

The results of fabrication of nanostructured La1−xSr
 x
 MnO3 films grown by pulsed injection metalorganic chemical vapour deposition technique onto special disordered glass-ceramics substrate are presented. Two groups of films were produced in order to determine what would be their main physical properties when certain fabrication changes were introduced: (1) films with thicknesses in the range of 25–900 nm, which were grown at a temperature of 750 °C; and (2) films having thicknesses of 400 nm, which were grown at different deposition temperatures ranging from 600 °C up to 775 °C in steps of 25 °C. It was determined that the morphology and microstructure of the films depends on the thicknesses of these films and their deposition temperatures. The thinnest films (25 nm) grew mainly in amorphous phase, while the thicker films had well-pronounced structure made of column-shaped crystallites. These had average column widths of 40–65 nm, were spread throughout the whole thickness of the films, and were separated by 5–10-nm-thick grain boundaries. The influence of growth conditions on the colossal magnetoresistance effect in these films was studied in pulsed magnetic fields of up to 20 T. The dependences of the magnetoresistance on the magnetic flux density were analysed using modified Mott’s hopping model. It was demonstrated that these nanostructured films behave as superparamagnetic materials with reduced magnetic properties due to disordered grain boundaries. The obtained results allow the tuning of the resistivity, magnetoresistance and the anisotropy of La1−xSr
 x
 MnO3 manganite films, which were deposited onto glass-ceramic substrates, and thus to use them for the fabrication of high pulsed magnetic field sensors.

Magnetoresistive properties of thin nanostructured manganite films grown by metalorganic chemical vapour deposition onto glass-ceramics substrates

This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The proposed LC DCO consisted of the following main blocks: the high Q-factor inductor, switched-capacitors block, cross-coupled transistors, and the current control block. Inductors with switched-capacitors block formed an LC tank. The designed E-TSPC frequency divider consisted of eight blocks connected in a series; each block increased the division ratio by a factor of two. The frequency of the input signal was divided in the region from two to 256 times using the designed divider. The main parameters of the designed E-TSPC divider and the LC DCO measurements were given as follows: LC DCO achieved a wide tuning range from 10.25 GHz to 11.78 GHz (1.53 GHz, 15.28% bandwidth); phase noise at 1 MHz offset frequency from LC DCO lowest carrier frequency was −113.42 dBc/Hz; phase noise at 1 MHz offset frequency from LC DCO highest carrier frequency was −110.51 dBc/Hz; The average power consumption of the designed LC DCO core and E-TSPC divider were 10.02 mW and 97.52 mW, respectively; the figure of merit (FOM) and the extended FOMT values of the proposed LC DCO were −183.52 dBc/Hz and −187.20 dBc/Hz, respectively. These FOM and FOMT results were achieved due to very low phase noise (−113.52 dBc/Hz) and a wide frequency tuning range (15.28%). The total layout area including the pads was 1.5 mm × 1.5 mm, with the largest part of the layout occupied by the proposed LC DCO (193 µm × 311 µm). The largest part of the LC DCO was occupied by the inductor 184 µm × 184 µm. The manufactured chip was packed into a quad flat no-leads (QFN) 20 pads package.

https://www.mdpi.com/2079-9292/8/1/72/pdf

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

This paper reviews CMOS LC Voltage Controlled Oscillators (VCO) for wireless multi-standard transceivers and wireless communications. The main parameters, such as phase noise, carrier frequency, supply voltage, tuning range, power dissipation, figure of merit (FOMt) were reviewed in this paper.

Romualdas Navickas

Papers

Review of V2X–IoT Standards and Frameworks for ITS Applications

Reverse engineering of CMOS integrated circuits

Magnetoresistive properties of thin nanostructured manganite films grown by metalorganic chemical vapour deposition onto glass-ceramics substrates

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

CMOS technology based LC VCO review