Flip/flop

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Apparatuses and methods for performing compare operations using sensing circuitry

Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

Division operations for memory

Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

Independently addressable memory array address spaces

A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signal based on the clock signal and the first and second input signals. The delay stage is operatively coupled to the input and output stages. The delay stage includes a first and second branch. The second branch includes at least one more delay element than the first branch.

Sense amplifier based flip-flop

A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Scan flip-flop with internal latency for scan input

Static timing analysis (STA) techniques allow a designer to check the timing of a circuit at different process corners, which typically include corner values of the supply voltages as well. Traditionally, however, this analysis only considers cases where the supplies are either all low or all high. As will be demonstrated, this may not yield the true maximum delay of a circuit because it neglects the possible mismatch between the supplies of successive gates on a path. A new methodology for timing analysis is proposed, where, in a first step, the critical paths of a circuit are identified under an assumption that all the supply nodes are independent of one another, thus allowing for mismatch between the supplies. Then, given these critical paths, the authors incorporate into the analysis the relationships between the supply node voltages by considering the power grid that they are tied to, and refine the worst case time delay values on a per-critical-path basis. This refinement is posed as a sequence of optimization problems where the operation of the circuit is abstracted in terms of current constraints. The authors present their technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids

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Voltage-Aware Static Timing Analysis

A new single ended sense-amplifier based flip-flop is proposed whose the sense amplifier stage is modified such that a balanced rise/fall delay is achieved. The new flip-flop has a comparable timing characteristic of a Master-Slave latch with 25% power reduction. The proposed flip flop has the same transistor count as the peer Master-Slave flop which is widely used in current standard cell libraries. The proposed flop can be swapped with normal flop after synthesis or can be used in the early synthesis stage to save power without any area or timing penalty.

A Low Power Sense Amplifier Flip-Flop With Balanced Rise/Fall Delay

A system and method are provided for measuring an integrated circuit age. A first clock generator is provided for generating a first dock signal. Additionally, a second clock generator is provided for generating a second clock signal. Further, a phase detector is provided that is in communication with the first dock generator and the second dock generator. The phase detector is operable for receiving the first clock signal from the first clock generator and the second clock signal from the second dock generator, and outputting a phase difference signal. Still yet, a circuit is provided that is in communication with the phase detector and the first clock generator. The circuit is operable for receiving the first clock signal from the first clock generator and the phase difference signal from the phase detector. The circuit is further operable for synchronizing the phase difference signal from the phase detector with the first dock signal from the first clock generator. Moreover, the phase difference signal is capable of being used as a measure of an integrated circuit age.

Rubil Ahmadi

Papers

Sense amplifier based flip-flop

Scan flip-flop with internal latency for scan input

Voltage-Aware Static Timing Analysis

A Low Power Sense Amplifier Flip-Flop With Balanced Rise/Fall Delay

System and method for measuring an integrated circuit age