A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Characterization adn reduction of variation for integrated circuits

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Characterization and verification for integrated circuit designs

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Dummy fill for integrated circuits

Use of models in integrated circuit fabrication

A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process. A location on an integrated circuit is predicted for which a lithography tool would not produce a satisfactory feature dimension without a degree of adjustment of the tool during fabrication to accommodate a focus limitation of the tool, and the design of at least one mask derived from the design is adjusted to enable the lithography tool to produce a satisfactory feature dimension at the locations. A virtual adjustment is effected of a distance of a lithographic tool from a location in a region of a wafer, the virtual adjustment being effected by using a mask having a mask layout that has been generated based on a pattern-dependent model prediction that the location in the region of the wafer would not otherwise have a satisfactory feature dimension due to a focus limitation of the lithographic tool. A pattern-dependent model is used to predict topography variations that will occur in an integrated circuit as a result of processing up to a predetermined lithographic process step, and designs of masks used in the lithographic process step are adjusted to accommodate the topography variations.

Adjustment of masks for integrated circuit fabrication

In a trench-first-via-last (TFVL) dual-inlaid metal process, the thickness of resist coated in the via definition step after trench formation varies according to underlying trench topography Variation in resist thickness reduces via size uniformity and thus process window Based on the modeling of resist thickness at a via location as a weighted sum of nearby trench densities, layout modifications of proximity dummy feature placement and selective via sizing are introduced to increase via size uniformity Experimental results show significantly enlarged process window after proximity dummy features are inserted

Proximity dummy feature placement and selective via sizing for process uniformity in a trench-first-via-last dual-inlaid metal process

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Semiconductor device and a process for designing a mask

A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

Method of forming an integrated circuit device using dummy features and structure thereof

Method for adding features to a design layout and process for designing a mask

In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An isolation zone is provided around active features. A scanning process of the feature layout surveys oxide density and nitride density over the wafer layer outside of said isolation zone. Values of the ratios of oxide/nitride density for two or more length scales which define tiling zones, are calculated. Tile placement and sizing in the zones is dependent upon the oxide/nitride density ratio values; and further upon an oxide deposition model specific to the oxide used in the fabrication process and upon a polishing model of the CMP process being employed.

Ruiqi Tian

Papers

Proximity dummy feature placement and selective via sizing for process uniformity in a trench-first-via-last dual-inlaid metal process

Semiconductor device and a process for designing a mask

Method of forming an integrated circuit device using dummy features and structure thereof

Method for adding features to a design layout and process for designing a mask

Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems