A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Methods for multi-wire routing and apparatus implementing same

A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.

Methods for cell phasing and placement in dynamic array architecture and implementation of the same

A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned.

Finfet transistor circuit

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect

In a trench-first-via-last (TFVL) dual-inlaid metal process, the thickness of resist coated in the via definition step after trench formation varies according to underlying trench topography Variation in resist thickness reduces via size uniformity and thus process window Based on the modeling of resist thickness at a via location as a weighted sum of nearby trench densities, layout modifications of proximity dummy feature placement and selective via sizing are introduced to increase via size uniformity Experimental results show significantly enlarged process window after proximity dummy features are inserted

Proximity dummy feature placement and selective via sizing for process uniformity in a trench-first-via-last dual-inlaid metal process

A comparison of via overetch is made between a conventional integration using aluminum interconnects plus tungsten via plugs and a dual-inlaid integration using copper. Excessive overetch for Al interconnects can cause reliability problems because of veil formation, as well as create very high aspect ratio recesses that are difficult to fill. The reasons for variation in interlevel dielectric (ILD) thickness and via etch rate are discussed. For the Al-W interconnect system, oxide CMP controls the ILD thickness. In addition, the via etch rate has been observed to drop over time. Both contribute significant variations to via overetch. For a via-first dual-inlaid integration, the ILD deposition determines the via depth uniformity. In metal-first dual-inlaid, the metal trench etch controls the via depth. In both cases, the via etch rate has been optimized to be more stable over time. Overall, the Al-W integration has a very wide range of via depths and etch rates that must be tolerated, whereas the dual-inlaid integrations have only a few percent of variation.

A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations

A modular 0.25 /spl mu/m CMOS core technology suitable for high density and high-performance or low-power applications is presented. The key salient features include: simple 1-mask STI, 40 /spl Aring/ high-performance or low-power CMOS transistor modules, cobalt salicide, a practical 2D Optical Proximity Correction (OPC) technique applied to tight-pitch local interconnect and 6-level tiled metallization backend that include unlanded vias and no-cap Inter-Level Dielectric (ILD). This technology is capable of producing state-of-the-art 380 MHz RISC microprocessors (47 mm/sup 2/) with 9.4 /spl mu/m/sup 2/ 6 T bitcell SRAM. The modularity of the process architecture allows the subsequent expansion of the integration to a wide-range of applications.

S. Chheda

Papers

Proximity dummy feature placement and selective via sizing for process uniformity in a trench-first-via-last dual-inlaid metal process

A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations

A manufacturable and modular 0.25 /spl mu/m CMOS platform technology