http://www.inf.ufrgs.br/logics/docman/presentation_mej_testchip.pdf

Contributions to the evaluation of ensembles of combinational logic gates

A design platform (DP) is a total solution to build a System-On-Chip (SOC). DP consists of a set of libraries/IPs, CAD tools and design kits in conformity with the supported design flows and methodologies. The DP specifications provide a wide range of information from technology parameters like Process-Voltage-Temperature (PVT) corners to CAD tools’ information for library/IP development. However, the library/IP developers have difficulties in obtaining the desired data from the existing specifications due to their informality and complexity. In this thesis, we propose methodologies, flows and tools to formalize the DP specifications for their unification and to deal with it. The proposed description is targeting to be used as a reference to generate and validate libraries (standard cells, I/O, memory) as well as complex IPs (PLL, Serdes, etc.). First, we build a suitable data model to represent all required information for library/IP development and then propose a specification language named Library Development Specification based on XML (LDSpecX). Furthermore, we introduce a reference-based method to create a reliable specification in LDSpecX and task-based keywords to efficiently extract data from it. On the basis of the proposed solutions, we develop a specification platform. Experimentally, we develop a standard cell library from the specification creation to library validation by using the specification platform. We show that our approach enables to create a complete and consistent specification with a considerable reduction in time. It also bridges the gap between the specification and current automatic system for rapid library/IP development.

https://tel.archives-ouvertes.fr/tel-01126920/document

Specification Platform for Library IP Development

Une plateforme de conception est une solution totale qui permet a une equipe de conception de developper un systeme sur puce. Une telle plateforme se compose d'un ensemble de bibliotheques et de circuits reutilisables (IPs), d'outils de CAO et de kits de conception en conformite avec les flots de conception et les methodologies supportes. Les specifications de ce type de plateforme offrent un large eventail d'informations, depuis des parametres de technologie, jusqu'aux informations sur les outils. En outre, les developpeurs de bibliotheque/IP ont des difficultes a obtenir les donnees necessaires a partir ces specifications en raison de leur informalite et complexite. Dans cette these, nous proposons des methodologies, des flots et des outils pour formaliser les specifications d'une plateforme de conception et les traiter. Cette description proposee vise a etre utilisee comme une reference pour generer et valider les bibliotheques et les IPs. Nous proposons un langage de specification base sur XML (nomme LDSpecX). De plus, nous presentons une methode basee sur des references pour creer une specification fiable en LDSpecX et des mots-cles bases sur des tâches pour en extraire les donnees efficacement. A l'aide des solutions proposees, nous developpons une plateforme de specification. Nous developpons une bibliotheque de cellules standard en utilisant cette plateforme de specification. Nous montrons ainsi que notre approche permet de creer une specification complete et coherente avec une reduction considerable du temps. Cette proposition comble egalement l'ecart entre les specifications et le systeme automatique existant pour le developpement rapide de bibliotheques/IPs.

/pdf/plateforme-de-specification-pour-le-developpement-de-2ymygs2tjl.pdf

Plateforme de spécification pour le développement de bibliothèques de cellules et d'IPs

This work proposes a simple, efficient and easy-touse test circuit for evaluating and validating any set of logic gates in terms of functionality, performance, power consumption and impact in operation of sub-nanometer physical effects.

/pdf/efficient-test-circuit-to-qualify-logic-cells-94uk6bwqcy.pdf

Efficient test circuit to qualify logic cells

This work presents the validation in silicon of a test chip for the evaluation of ensembles of combinational CMOS gates (cell library) The design methodology and the architecture of this simple, efficient and easy-to-use test circuit were already proposed theoretically in the past, having been demonstrated its functionality only through partial electrical simulations The fabrication and measurements over on-silicon prototype provide important information about design improvement possibilities of such a test circuit and its architecture The results are presented and discussed in this paper

On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design

The experience of designing and employing two benchmark circuits to improve the quality of a standard cell library is reported. It is found that most of the errors can be uncovered by making use of these two benchmark circuits to port the underlying cell library to the target environment. Two releases of a 0.25 /spl mu/m standard cell library have been tested by these two benchmark circuits to ensure their quality.

/pdf/benchmark-circuits-improve-the-quality-of-a-standard-cell-32dnmsn8pm.pdf

Rung-Bin Lin

Papers

Benchmark circuits improve the quality of a standard cell library