Showing papers by "Runsheng Wang published in 2006"

New insights into oxide traps characterization in gate-all-around nanowire transistors with TiN metal gates based on combined I g -I d RTS technique

Abstract: By using combined gate current and drain current random telegraph signal noise (I g -I d RTS) technique, both electron and hole traps within the gate stack of silicon nanowire transistors (SNWTs) with TiN metal gates are experimentally studied in this paper. For the first time, I g RTS is observed in p-SNWTs, which originated from electron traps that are induced by multiple crystal orientations of the cylindrical channel. While I d RTS is found to be related to hole traps in p-SNWTs. Therefore, it is demonstrated that this combined I g -I d RTS technique can be used to separately investigate the properties of electron and hole traps in SNWTs and other advanced MOSFETs. Based on corrected RTS model for gate-all-around (GAA) SNWT structure, the locations, time constant, activation energy and capture cross sections of traps in SNWTs are extracted. In addition, the results indicate that Id RTS in SNWT is caused by two kinds of oxide hole traps. One is weak structural dependent trap and the other is strong structural dependent trap, which originates from the enhanced quantum confinement in nanowire structures.