R
Russell M. Clapp
Researcher at Intel
Publications - 11
Citations - 502
Russell M. Clapp is an academic researcher from Intel. The author has contributed to research in topics: Cache & Cache pollution. The author has an hindex of 8, co-authored 11 publications receiving 496 citations. Previous affiliations of Russell M. Clapp include IBM & Business International Corporation.
Papers
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Proceedings ArticleDOI
STiNG: A CC-NUMA Computer System for the Commercial Marketplace
Tom Lovett,Russell M. Clapp +1 more
TL;DR: The motivation for building STiNG as well as its architecture and implementation are described, and performance analysis is provided for On-Line Transaction Processing (OLTP) and Decision Support System (DSS) workloads.
Patent
Fabric-Backplane Enterprise Servers with Pluggable I/O Sub-System
Daniel H. Bax,William Jackson Bibb,Russell M. Clapp,Tom Gourley,Geoffrey H. Hanson,Allen Hirashiki,Thomas Dean Lovett,Sharad Mehrotra,Shyam Mittur,Nakul Pratap Saraiya +9 more
TL;DR: A cost-reduced enterprise server (CRES) system includes a flexible resource-efficient server having a plurality of Processor Memory Boards (PMBs) coupled to an Input/Output Module (IOM), which provides all networking and storage interfaces for the server as discussed by the authors.
Patent
Implementation-efficient multiple-counter value hardware performance counter
TL;DR: In this article, an implementation-efficient, multiple-counter value hardware performance counter is presented, which stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond.
Proceedings ArticleDOI
Quantifying the Performance Impact of Memory Latency and Bandwidth for Big Data Workloads
TL;DR: This work presents straightforward analytic equations to quantify the impact of memory bandwidth and latency on workload performance, and demonstrates how the values of the components of these equations can be used to classify different workloads according to their inherent bandwidth requirement and latency sensitivity.
Patent
Caching memory contents into cache partitions baesed on memory locations
TL;DR: In this paper, a location of a line of memory to be cached in a cache is determined, and the cache is partitioned into a number of cache sections based on the location of the line.