Choosing the correct error injection technique is of primary importance in simulation-based design and evaluation of robust systems that are resilient to soft errors. Many low-level (e.g., flip-flop-level) error injection techniques are generally used for small systems due to long execution times and significant memory requirements. High-level error injections at the architecture or memory levels are generally fast but can be inaccurate. Unfortunately, there exists very little research literature on quantitative analysis of the inaccuracies associated with high-level error injection techniques. In this paper, we use simulation and emulation results to understand the accuracy trade-offs associated with a variety of high-level error injection techniques. A detailed analysis of error propagation explains the causes of high degrees of inaccuracies associated with error injection techniques at higher levels of abstraction.

Quantitative evaluation of soft error injection techniques for robust system design

The objective of IFRA, Instruction Footprint Recording and Analysis, is to overcome the challenges associated with a very expensive step in post-silicon validation of processors -- bug localization in a system setup. IFRA consists of special design and analysis techniques required to bridge a major gap between system-level and circuit-level debug. Special hardware recorders, called Footprint Recording Structures (FRS's), record semantic information about data and control flows of instructions passing through various design blocks of a processor. This information is recorded concurrently during normal operation of a processor in a post-silicon system validation setup. Upon detection of a problem, the recorded information is scanned out and analyzed for bug localization. Special program analysis techniques, together with the binary of the application executed during post-silicon validation, are used for the analysis. IFRA does not require full system-level reproduction of bugs or system-level simulation. Simulation results on a complex super-scalar processor demonstrate that IFRA is effective in accurately localizing bugs with very little impact on overall chip area.

IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors

Instruction Footprint Recording and Analysis (IFRA) overcomes challenges associated with an expensive step in post-silicon validation of processors-pinpointing the bug location and the instruction sequence that exposes the bug from a system failure. On-chip recorders collect instruction footprints (information about flows of instructions and what the instructions did as they passed through various design blocks) during the normal operation of the processor in a post-silicon system validation setup. Upon system failure, the recorded information is scanned out and analyzed offline for bug localization. Special self-consistency-based program analysis techniques, together with the test program binary of the application executed during post-silicon validation, are used for this purpose. Major benefits of using IFRA over traditional techniques for post-silicon bug localization are as follows: 1) it does not require full system-level reproduction of bugs, and 2) it does not require full system-level simulation. Simulation results on a complex superscalar processor demonstrate that IFRA is effective in accurately localizing electrical bugs with very little impact on overall chip area.

Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)

As of 2013, the gold standard for assessing radiation-hardness assurance (RHA) for a system, subsystem, or a component is accelerated radiation testing and/or pulsed laser testing. Fault injection tools, which include both fault simulation and emulation tools, have become more common in the last 15 years. Fault simulation tools use analytical methods for assessing RHA, whereas fault emulation uses hardware methods. Both fault simulation and emulation allow designers to augment traditional RHA techniques to determine whether circuit designs, microarchitectures, components, and application-specific integrated circuits (ASICs) meet the requirements for a particular mission. Fault simulation and emulation can provide the designers the luxury of testing on the benchtop without the time and financial constraints of accelerated radiation testing. This paper explores how to design, implement, and validate a fault simulation or emulation system. The paper ends with several case studies of currently used fault simulation and emulation systems.

Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing

A method for statistical fault injection (SFI) into arbitrary latches within a full system hardware-emulated model is validated against particle-beam-accelerated SER testing for a modern microprocessor. As performed on the IBM POWER6 microprocessor, SFI is capable of distinguishing between error handling states associated with the injected bit flip. Methodologies to perform random and targeted fault injection are presented.

Statistical Fault Injection

The error detection and correction capability of the IBM POWER6™ processor enables high tolerance to single-event upsets. The soft-error resilience was tested with proton beam- and neutron beam-induced fault injection. Additionally, statistical fault injection was performed on a hardware-emulated POWER6 processor simulation model. The error resiliency is described in terms of the proportion of latch upset events that result in vanished errors, corrected errors, checkstops, and incorrect architected states.

Soft-error resilience of the IBM POWER6 processor

A modular computing housing includes a housing structure having a plurality of component slots that each can receive one of a plurality of components, where at least one of the components includes a processor having an operating frequency. A cooling system provides airflow through each of said component slots. A thermal control system can be communicably connected to each of the component slots and each of the received component processors. When the thermal control system receives configuration data from each of the component slots, retrieves throttle data corresponding to the configuration data and directs at least one received component processors to reduce its operating frequency in accordance with the throttle data.

Ryan B. McBeth

Papers

Soft-error resilience of the IBM POWER6 processor

Preemptive Thermal Control by Processor Throttling in a Modular Computing System