High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

IEEE International Solid-State Circuits Conference

Computational Science and Engineering (CSE) is the multi-disciplinary field of computer-based modelling and simulation for studying scientific phenomena and engineering designs. Modelling and simulation helps to validate theory, and makes it possible to analyse scenarios that would otherwise be too time-consuming, expensive, or dangerous to study by experiment. Data exploration helps to turn numbers into insight which is especially challenging in times of Big Data.

Computational Science and Engineering

A classic problem is the estimation of a set of parameters from measurements collected by only a few sensors. The number of sensors is often limited by physical or economical constraints and their placement is of fundamental importance to obtain accurate estimates. Unfortunately, the selection of the optimal sensor locations is intrinsically combinatorial and the available approximation algorithms are not guaranteed to generate good solutions in all cases of interest. We propose FrameSense, a greedy algorithm for the selection of optimal sensor locations. The core cost function of the algorithm is the frame potential, a scalar property of matrices that measures the orthogonality of its rows. Notably, FrameSense is the first algorithm that is near-optimal in terms of mean square error, meaning that its solution is always guaranteed to be close to the optimal one. Moreover, we show with an extensive set of numerical experiments that FrameSense achieves state-of-the-art performance while having the lowest computational cost, when compared to other greedy methods.

Near-Optimal Sensor Placement for Linear Inverse Problems

Asymmetric multi-core architectures integrating cores with diverse power-performance characteristics is emerging as a promising alternative in the dark silicon era where only a fraction of the cores on chip can be powered on due to thermal limits. We introduce a hierarchical power management framework for asymmetric multi-cores that builds on control theory and coordinates multiple controllers in a synergistic manner to achieve optimal power-performance efficiency while respecting the thermal design power budget. We integrate our framework within Linux and implement/evaluate it on real ARM big.LITTLE asymmetric multi-core platform.

/pdf/hierarchical-power-management-for-asymmetric-multi-core-in-ot2wjklk4t.pdf

Hierarchical power management for asymmetric multi-core in dark silicon era

The ability to cap peak power consumption is a desirable feature in modern data centers for energy budgeting, cost management, and efficient power delivery. Dynamic voltage and frequency scaling (DVFS) is a traditional control knob in the tradeoff between server power and performance. Multi-core processors and the parallel applications that take advantage of them introduce new possibilities for control, wherein workload threads are packed onto a variable number of cores and idle cores enter low-power sleep states. This paper proposes Pack & Cap, a control technique designed to make optimal DVFS and thread packing control decisions in order to maximize performance within a power budget. In order to capture the workload dependence of the performance-power Pareto frontier, a multinomial logistic regression (MLR) classifier is built using a large volume of performance counter, temperature, and power characterization data. When queried during runtime, the classifier is capable of accurately selecting the optimal operating point. We implement and validate this method on a real quad-core system running the PARSEC parallel benchmark suite. When varying the power budget during runtime, Pack & Cap meets power constraints 82% of the time even in the absence of a power measuring device. The addition of thread packing to DVFS as a control knob increases the range of feasible power constraints by an average of 21% when compared to DVFS alone and reduces workload energy consumption by an average of 51.6% compared to existing control techniques that achieve the same power range.

http://www.bu.edu/dbin/ece/people/acoskun/cochran_MICRO11.pdf

Pack & Cap: adaptive DVFS and thread packing under power caps

The increased power densities of multi-core processors and the variations within and across workloads lead to runtime thermal hot spots locations of which change across time and space. Thermal hot spots increase leakage, deteriorate timing, and reduce the mean time to failure. To manage runtime thermal variations, circuit designers embed within-die thermal sensors that acquire temperatures at few selected locations. The acquired temperatures are then used to guide runtime thermal management techniques. The capabilities of these techniques are essentially bounded by the spatial thermal resolution of the sensor measurements. In this paper we characterize temperature signals of real processors and demonstrate that on-chip thermal gradients lead to sparse signals in the frequency domain. We exploit this observation to (1) devise thermal sensor allocation techniques, and (2) devise signal reconstruction techniques that fully characterize the thermal status of the processor using the limited number of measurements from the thermal sensors. To verify the accuracy of our methods, we compare our temperature characterization results against thermal measurements acquired from a state-of-the-art infrared camera that captures the mid-band infrared emissions from the back of the die of a 45 nm dual-core processor. Our results show that our techniques are capable of accurately characterizing the temperatures of real processors.

Thermal monitoring of real processors: techniques for sensor allocation and full characterization

Elevated temperatures impact the performance, power consumption, and reliability of processors, which rely on integrated thermal sensors to measure runtime thermal behavior. These thermal measurements are typically inputs to a dynamic thermal management system that controls the operating parameters of the processor and cooling system. The ability to predict future thermal behavior allows a thermal management system to optimize a processor's operation so as to prevent the on-set of high temperatures. In this paper we propose a new thermal prediction method that leads to consistent results between the thermal models used in prediction and observed thermal sensor measurements, and is capable of accurately predicting temperature behavior with heterogenous workload assignment on a multicore platform. We devise an off-line analysis algorithm that learns a set of thermal models as a function of operating frequency and globally defined workload phases. We incorporate these thermal models into a dynamic voltage and frequency scaling (DVFS) technique that limits the maximum temperature during runtime. We demonstrate the effectiveness of our proposed system in predicting the thermal behavior of a real quad-core processor in response to different workloads. In comparison to a reactive thermal management technique, our predictive method dramatically reduces the number of thermal violations, the magnitude of thermal cycles, and workload runtimes.

Consistent runtime thermal prediction and control through workload phase detection

Hot spots are a major concern in high-end processors as they constrain performance and limit the lifetime of semiconductor chips. Using embedded thermal sensors, dynamic thermal management systems track the hot spots during runtime and adjust the performance and the cooling system of the processor when necessary. In many-core processors, the locations of hot spots vary spatially and temporally depending on the configuration of active cores and the workloads running on the cores. Our work includes both theoretical advances in sensor allocation techniques and experimental advances for thermal imaging of real processors. We propose a hard sensor allocation algorithm to determine the sensor locations where hot spots can be tracked accurately given a budget number of sensors. We also propose soft sensor computation techniques to alleviate design constraints on sensor locations and to further improve the resolution of hot spot tracking. The proposed soft sensing technique combines the measurements of the hard sensors in an optimal way to estimate the temperature at any desired location. We use infrared imaging methods to characterize the thermal behavior of a real dual-core processor during operation. We execute large number of workload configurations on the processor and track the locations and temperatures of hot spots during runtime. The thermal characterization data are then used as the input to our sensor allocation techniques. We demonstrate that our sensor allocation techniques improve significantly upon the previous results in the literature and provide accurate tracking of hot spots.

Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques

Elevated chip temperatures are true limiters to the scalability of computing systems. Excessive runtime thermal variations compromise the performance and reliability of integrated circuits. To address these thermal issues, state-of-the-art chips have integrated thermal sensors that monitor temperatures at a few selected die locations. These temperature measurements are then used by thermal management techniques to appropriately manage chip performance. Thermal sensors and their support circuitry incur design overheads, die area, and manufacturing costs. In this paper, we propose a new direction for full thermal characterization of integrated circuits based on spectral Fourier analysis techniques. Application of these techniques to temperature sensing is based on the observation that die temperature is simply a space-varying signal, and that space-varying signals are treated identically to time-varying signals in signal analysis. We utilize Nyquist-Shannon sampling theory to devise methods that can almost fully reconstruct the thermal status of an integrated circuit during runtime using a minimal number of thermal sensors. We propose methods that can handle uniform and non-uniform thermal sensor placements. We develop an extensive experimental setup and demonstrate the effectiveness of our methods by thermally characterizing a 16-core processor. Our method produces full thermal characterization with an average absolute error of 0.6% using a limited number of sensors.

Ryan Cochran

Papers

Pack & Cap: adaptive DVFS and thread packing under power caps

Thermal monitoring of real processors: techniques for sensor allocation and full characterization

Consistent runtime thermal prediction and control through workload phase detection

Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques

Spectral techniques for high-resolution thermal characterization with limited sensor data