High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.

High aspect ratio silicon etch: A review

An intensive study has been performed to understand and tune deep reactive ion etch (DRIE) processes for optimum results with respect to the silicon etch rate, etch profile and mask etch selectivity (in order of priority) using state-of-the-art dual power source DRIE equipment. The
research compares pulsed-mode DRIE processes (e.g. Bosch technique) and mixed-mode DRIE processes (e.g. cryostat technique). In both techniques, an inhibitor is added to
fluorine-based plasma to achieve directional etching, which is formed out of an oxide-forming (O2) or a fluorocarbon (FC) gas (C4F8 or CHF3). The inhibitor can be introduced together with the etch gas, which is named a mixed-mode DRIE process, or the inhibitor can be added in a
time-multiplexed manner, which will be termed a pulsed-mode DRIE process. Next, the most convenient mode of operation found in this study is highlighted including some remarks to
ensure proper etching (i.e. step synchronization in pulsed-mode operation and heat control of the wafer). First of all, for the fabrication ......
 Enjoy reading . Henri Jansen 18 June 2008

https://iopscience.iop.org/article/10.1088/0960-1317/19/3/033001/pdf

Black silicon method X: a review on high speed and selective plasma etching of silicon with profile control: an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next generation equipment

The evolution of silicon cryoetching is reported in this topical review, from its very first introduction by a Japanese team to today's advanced technologies. The main advances in terms of the performance and comprehension of the mechanisms are chronologically presented. After presenting the principle of silicon cryoetching, the main defects encountered in cryoetching (such as undercut, bowing and crystal orientation dependent etching) are presented and discussed. Mechanisms involved in SiOxFy passivation layer growth in standard cryoetching are investigated through several in situ characterization experiments. The STiGer process and alternative cryoetching processes for high-aspect-ratio structures are also proposed to enhance the process robustness. The over-passivation regime, which can provide self-organized columnar microstructures, is presented and discussed. Finally, advanced technologies, such as the cryoetching of sub-20 nm features and porous OSG low-k cryoetching, are described.

https://iopscience.iop.org/article/10.1088/0022-3727/47/12/123001/pdf

Plasma cryogenic etching of silicon: from the early days to today's advanced technologies

A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Through-wafer interconnects for photoimager and memory wafers

Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

Packaged microelectronic imagers and methods of packaging microelectronic imagers

We are interested in etching very deep anisotropic trenches (∼100 μm) with high aspect ratios (depth/width) (∼20–50) and high etch rates (∼5 μm/min). A high density plasma helicon reactor using SF6/O2 chemistry and a cryogenic chuck has been used for etching very narrow trenches from 1.2 to 10 μm wide on n-type Si wafers with a SiO2 mask. The first results show significant features that demonstrate the feasibility of this method. Two-micron-wide trenches have been etched to a depth of 80 μm at an average etch rate of 2.7 μm/min. The resulting profiles are highly anisotropic and selectivity of Si/SiO2 is remarkably high (>500).

S. Aachboun

Papers

Deep anisotropic etching of silicon