A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

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3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. 

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. 

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.




* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Three-Dimensional Integrated Circuit Design

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Dense arrays and charge storage devices

Monolithic three dimensional array of charge storage devices containing a planarized surface

The process technologies for realizing a 3-D LSI are reported with emphasizing the high quality laser recrystallization and the thermally stable interconnects. A homogeneous recrystallization of the silicon island array was achieved all over a wafer by the dual laser beam recrystallization method (DLB), in which the 2-dimensional energy distribution of the laser beam was precisely controlled. Thermally stable interconnects in the 1st layer were realized by W wiring and stoichiometry controlled W/WSi/Si contact structure. By these key technologies, the 8-kbit CMOS SRAM with two-active layers has been fabricated. It was confirmed that these technologies were available to fabricate the 3-D LSI.

https://ieeexplore.ieee.org/iel5/9952/31972/01486470.pdf

Fabrication technologies for dual 4-kbit stacked SRAM

Multilayer CMOS devices were fabricated by a laser recrystallization technology. The single crystalline silicon islands embedded in an insulator on the top of MOS IC were studied. To minimize the thermal influence on a lower IC during the fabrication process, a CVD-SiO 2 was used as a retaining wall of silicon islands instead of a LOCOS. In addition, a planarized heat sink (PHS) polysilicon layer was employed to eliminate the impediment to a grain growth at the steps due to a lower IC. The single crystalline silicon islands were successfully obtained. The field effect mobility of NMOS transistors fabricated on single-crystallied silicon islands was calculated as about 400 cm2/V.sec, 490cm2/V.sec. The 10 bit CMOS shift register fabricated just on a lower IC was successfully operated at V DD =6.5 V, f CLK = 1 MHz. The 4 bit CMOS shift register, stacking PMOS on NMOS was also successfully operated.

Multilayer CMOS device fabricated on laser recrystallized silicon islands

A half inch size CCD area imaging device having the structure of the Photoconductive-Layer-On-Solid -Scanner(PLOSS) has been designed and fabricated for investigating the capability of applying the very small size image sensor to the compact-video-camera. A buried channel CCD is used as a scanner. A narrow and a short channel effects on the CCD potential well are also evaluated. As a sensor, ZnSe-ZnCdTe photoconductor is employed and vacuum-deposited on the CCD scanner to use the whole area on a Si chip as a photosensitive area. The device is designed for minimum size effect. The experimental device has 375(H) × 482(V) picture elements in the imaging area of 6.4(H) mm × 4.8(V) mm. The maximum handling charge of the CCD register is 1.7 × 105electrons/packet. The saturation signal current is 160 nA. The sensitivity of the device with the IR-cut filter is 0.018 µA/1ux. The SN ratio is above 60 dB(FPN). The blooming phenomenon is suppressed up to 150 times as intense as the saturation exposure within the 10 % smearing signal.

A CCD imaging device having a PLOSS structure

Introduction In the past few years, Imaging Devices(IDs) have been pioneering devices in a 256K bit VLSI field, since ID have over 200K picture elements. Various type of IDs such as IL-CCD, MOS and oveTlay sensor ID have been reported (1)-(4). These IDs have about 200K picture elements in the 2/3 inch lens view field of 0.67 cm2. On the other hand, recent 256K bit dRAMs are built in an array area of about 0.3 cm2 (5)-(7). As summarized in Table 1, ID and dRAM have many other features in common such as large array size, small signal of the order of 105-106 electrons per packet,-dynamic charge storage in 4-33 msec and the simplified cell structure. However, noise problem is more severe in IDs than dRAMs. Signal to fixed pattern noise(FPN) ratio of about 60dB is necessary for ID. The ratio becomes more critical in a half inch size overlay sensor ID we have develop5d (8). The device has the array area of 0.34 cm which is much the same size of the array area of the 256K bit dRAMI This paper describes FPN throughout the wafer caused by the dark current and its spikes which affect on the dynamic range in IDs and the maximum storage time.

S. Akiyama

Papers

Fabrication technologies for dual 4-kbit stacked SRAM

Multilayer CMOS device fabricated on laser recrystallized silicon islands

A CCD imaging device having a PLOSS structure

An Imaging Device as a VLSI

Characteristics of micro-groove zone-melting recrystallised Si islands