An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

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3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Nonplanar transistors with metal gate electrodes

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. 

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. 

This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.




* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult to find;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Three-Dimensional Integrated Circuit Design

A resonant electron transfer device includes a plurality of units each of which has of at least one one-dimensional quantum wire having a quantum well elongated in a direction, a zero-dimensional quantum dot having a base quantization level higher than that of the one-dimensional quantum wire an electrode for controlling respective internal levels of the quantum wire and dot wherein the quantum wire and dot forming one unit is connected via a potential barrier capable of exhibiting a tunnel effect therebetween.

Resonant electron transfer device

A silicon substrate comprises at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from the surfaces, and an electrically conductive portion insulated electrically by the electrically insulating layer from an outside of the silicon substrate.

Method of producing electrically insulated silicon structure

The method of fabricating a quantum device of the invention includes the steps of: forming a quantum dot having side faces on a first insulating layer; forming a second insulating layer which can function as a tunnel film, on at least the side faces of the quantum dot; depositing a non-crystal semiconductor layer on the first insulating layer so as to cover the quantum dot; removing at least a portion of the non-crystal semiconductor layer which is positioned above the quantum dot; single-crystallizing a predetermined portion of the non-crystal semiconductor layer which is in contact with the second insulating layer; and forming a quantum wire which includes the single-crystallized semiconductor portion and the quantum dot, on the first insulating layer.

Method of fabricating a quantum device

The process technologies for realizing a 3-D LSI are reported with emphasizing the high quality laser recrystallization and the thermally stable interconnects. A homogeneous recrystallization of the silicon island array was achieved all over a wafer by the dual laser beam recrystallization method (DLB), in which the 2-dimensional energy distribution of the laser beam was precisely controlled. Thermally stable interconnects in the 1st layer were realized by W wiring and stoichiometry controlled W/WSi/Si contact structure. By these key technologies, the 8-kbit CMOS SRAM with two-active layers has been fabricated. It was confirmed that these technologies were available to fabricate the 3-D LSI.

https://ieeexplore.ieee.org/iel5/9952/31972/01486470.pdf

Fabrication technologies for dual 4-kbit stacked SRAM

A method of obtaining a multilayer semiconductor device by forming a semiconductor crystallized layer through an insulative material over a semiconductor substrate in which a semiconductor device is formed. The insulative material is formed on the semiconductor substrate in which the semiconductor device is fabricated and a first semiconductor layer is formed on the insulative material. Thereafter, the surface of the first semiconductor layer is planarized and an insulative material is formed on this planarized surface, then a second semiconductor layer is formed on this insulative material. Next, the second semiconductor layer is crystallized by the irradiation of an energy beam, thereby fabricating a device in the second crystallized semiconductor layer.

Terui Yasuaki

Papers

Resonant electron transfer device

Method of producing electrically insulated silicon structure

Method of fabricating a quantum device

Fabrication technologies for dual 4-kbit stacked SRAM

Method of manufacturing a multilayer semiconductor device