This paper summarizes the results of over 25 research groups or individual researchers that have presented video coding implementations on general-purpose processors with the new single instruction multiple data media instruction set architecture extensions. The extensions are introduced and the fundamentals for extensions, as well as some inherent problems, are explained. The reported attempts to utilize the extensions are divided into kernel- and application-level, as well as platform dependent and independent optimizations. Optimized applications include, in addition to some proprietary methods, all of the major video coding standards such as H.261, H.263, MPEG-4, MPEG-1, and MPEG-2. These optimized implementations include a complete video codec, several decoders, and several encoders. Additionally, a performance comparison is given for four representative encoder implementations based on the reported results. Also included is an overview of future trends for new instructions and architectural speed-up techniques.

Overview of research efforts on media ISA extensions and their usage in video coding

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.

Reconfigurable Filter Coprocessor Architecture for DSP Applications

Numerical non-robustness is a recurring phenomenon in scientific computing. It is primarily caused by numerical errors arising because of fixed-precision arithmetic in integer and/or floating-point computations. Exact computation, based on arbitrary-precision arithmetic, has been developed over the last decade as an emerging numerical computation paradigm in response to this problem of numerical non-robustness. Exact arithmetic, specifically arbitrary-precision arithmetic, has been traditionally implemented using efficient software libraries such as GNU multi-precision (GMP). However, this results in a slower arithmetic performance when compared to fixed-precision arithmetic. In this paper we present a first effort, to the best of our knowledge, of reconfigurable hardware support for arbitrary-precision arithmetic. The proposed hardware architectures are based on virtual convolution scheduling which is derived from a formal representation of the problem. Targeting high performance and efficiency, dynamic (non-linear) pipelines techniques were exploited to eliminate the effects of deeply-pipelined operators. Referenced to GMP, our experiments showed promising results.

Bringing High-Performance Reconfigurable Computing to Exact Computations

Multithreading has been shown to be powerful approaches for boosting a system performance by taking advantage of parallelism in applications. Producer / Consumer, Web services, Banking and Image compression are good examples of applications that benefit from threading. Performance is increased because multiple threads running on multiple cores can process many requests simultaneously. This paper provides a summary of optimizing a serial designed application to multithreaded applications for Pentium dual core. The exercise uses the Java language as an example. This paper also discusses about the threading tool which is capable of converting a non threaded program into a threaded program to convert it into an efficient multithreaded application. It is observed that multithreading leads to tune the application performance considerably. To realize the advantages of model-driven development in designing parallel applications, a survey is conducted and it is observed that model driven development combined with multithreading can achieve better benefits .

Multithreading - An Efficient Technique for Enhancing Application Performance

Recent microprocessors have been enhanced with media instruction sets for accelerating media algorithms. They exploit the fact that media algorithms have small data types, and widths much less than that of the processor. Current media instruction sets support only 8-, 16- and 32-bit sub-datatypes. This scheme is inefficient in several applications where bit lengths of 9, 12 and so on are used. We need user programmable sub-datatype bit lengths. S. Balakrishnan and S.K. Nandy (1998) discuss arbitrary boundary packed addition. Many media algorithms are based on multiply-accumulate algorithms. For full acceleration we also need arbitrary boundary packed multiplication. We present such a scheme based on Wallace tree multiplication. We also expand on Balakrishnan and Nandy and provide a detailed treatment of the intermediate carries of sub-datatypes which were lost in the previous work. These carries could be used for saturation arithmetic and flow control.

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More on arbitrary boundary packed arithmetic

Current day general purpose processors have been enhanced with what is called "media instruction set" to achieve performance gains in applications that are media processing intensive. The instruction set that has been added exploits the fact that media applications have small native datatypes and have widths much less than that supported by commercial processors and the plethora of data-parallelism in such applications. Current processors enhanced with the "media instruction set" support arithmetic on sub-datatypes of only 8-bit, 16-bit, 32-bit and 64-bit precision. In this paper we motivate the need for arbitrary precision packed arithmetic wherein the width of the sub-datatypes are programmable by the user and propose an implementation for arithmetic on such packed datatypes. The proposed scheme has marginal hardware overhead over conventional implementations of arithmetic on processors incorporating a multimedia extended instruction set.

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Arbitrary precision arithmetic-SIMD style

In this paper, we present an architecture framework called SYMPHONY consisting of a linear array of processors that exploits parallelism in media applications at micro (ILP) and macro (threads) levels. High speed communication and synchronization necessary for efficient multitheading is achieved using novel hardware and software mechanisms. We demonstrate the efficacy of the SYMPHONY framework by performance evaluation of an instance in the framework. We show that multithreaded architectures coupled with SIMD parallelism provides performance improvement in excess of 2/spl times/ over conventional superscalar architectures.

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S. Balakrishnan

Papers

Arbitrary precision arithmetic-SIMD style

Performance evaluation of multithreaded architectures for media processing applications

Quasi dynamic approach to layout compaction