Compact Variation-Aware Standard Cell Models for Statistical Static Timing Analysis

Wire capacitance models used in some synthesis tools have been based on number of fanouts. These wire capacitance models can be misleading when compared to real wiring. This discrepancy can cause synthesis tools to optimize incorrectly causing severe problems with chip level timing convergence. Designs may take longer than expected and designers may work on timing paths that are not critical thus increasing the design cycle. In sub-micron designs it is crucial to improve the timing convergence between synthesis and physical design. This paper describes several practical approaches used in timing convergence of the IBM Gekko PowerPC/sup 1/ microprocessor that is used in the Nintendo Gamecube system. The impact of each approach is evaluated on the timing and size of the microprocessor.

S. Hojat

Papers

Techniques that improved the timing convergence of the Gekko PowerPC microprocessor