As analog and digital circuits have become more intertwined, we need to create a validation approach that handles both circuit types gracefully. This paper proposes a model-first approach, where one creates functional models of the analog blocks that will work in a HDL simulator, and then uses these models in the same way as HDL models are used for other standard cells: they are used in the full system validation, and the underlying implementations are validated to ensure they meet this specification. While creating functional models for the analog blocks might seem difficult, almost all analog blocks can be modeled as linear systems and we use this property to help create the required functional model.

Fortifying analog models with equivalence checking and coverage analysis

There is extensive evidence that the classical, stuck-at fault model, operating at the gate level, is inadequate for testing MOS VLSI circuits. By contrast, a ``nonclassical,'' switch-level model?directly representing open and short circuits in the interconnect and transistors stuck-open or stuck-on?allows important effects such as MOSFET bidirectionality and tristate behavior to be taken into account. This paper describes a new switch-level method for generating the singular cover of an MOS primitive gate using path algebras. The method yields tests to cover all specified interconnect open and short circuits, and all irredundant transistor stuck-open and stuck-on faults, should such tests exist. It relies on specification of an appropriate algebra by redefinition of the operators used in computing powers of a matrix. Two such algebras are required?one to generate tests for open circuit faults and the other for short circuit faults. Test generation for networks of primitive gates is achieved in two stages: after deriving singular covers for the primitives, a variant of the D-algorithm with modified ``D-drive'' is used. The approach is unified and powerful, having the potential to detect parasitic latch behavior and to generate tests for any of the current MOS VLSI technologies. In common with most present automatic test generation methods, it is restricted to combinational logic. Practical limits on the size of circuit which can be dealt with appear comparable to those set by use of the classical D-algorithm.

MOS Test Pattern Generation Using Path Algebras

In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus an two fault types: resistive bridges between gate outputs that cause pattern sensitive functional faults and opens in transmission gates that cause delay faults. In both cases, the traditional stuck at model is inadequate. The test vector to sensitize and propagate a resistive bridging fault is not unique. The traditional greedy test vector selection is optimistic, with some choices having poor real coverage. We realistically model the fault and fault coverage, and describe an optimal selection strategy. In a transmission gate with an open NMOS or PMOS device, the output voltage is degraded, increasing delay and reducing noise margin. We model this fault and show how low-voltage testing can be used to detect it. Our goal in applying these techniques to all important fault types is to maximize the real coverage of voltage tests, thereby minimizing the number of relatively slow Iddq tests required to achieve high quality.

http://ieeexplore.ieee.org/iel3/3739/10937/00510878.pdf

Optimal voltage testing for physically-based faults

A switch-level fault detection and diagnosis environment for MOS digital circuits using a compression data method based on a spectral signature is described. The selected fault model includes an MOS transistor permanently On and Off, breaks in internal gate lines, and shorts between two internal nodes of different logic gates, or between the internal nodes within the same complex gate. Circuit editing is performed in modules containing simple switch-level descriptions of the transistors. From the module structure a fault list is created, which will later be processed to eliminate all equivalent faults (fault collapsing). Simulation of the faults contained in this lift, and Walsh or Haar spectral analysis of the outputs, allow a data file to be created, containing a list of faults detected, a list of diagnosed fault groups and the spectral signature for each of these groups. The circuits are tested by comparing the information contained in this file and the data provided by a logic analysis system (LAS).<
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Switch-level fault detection and diagnosis environment for MOS digital circuits using spectral techniques

Reed-Muller coefficients are used to generate a test-pattern selection procedure for detecting single stuck-at faults. This procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults. The changes that the spectral coefficients undergo are also compared with the fault models used most frequently to model defects in combinational circuits. The proposed pattern-generating procedure does not need a simulation of the circuit for each of the possible stuck-at faults, and its complexity is proportional to the number of gates in the circuit. The proportionality constant increases exponentially as the number of inputs in the circuit increases. To evaluate the performance of the proposed method, its application to some benchmark circuits, including the ALU 74181, is presented. >

Test-pattern generation based on Reed-Muller coefficients

MOS VLSI circuits are often tested by using the stuck-at fault model to generate and evaluate test sequences that are intended to distinguish faulty from fault-free circuits. However, MOS circuits exhibit a wide variety of failure modes and there is no guarantee that the model accurately reflects the ways in which they fail. The paper gives many examples of faults taken from faulty NMOS circuits and discusses their associated fault-effects on a typical NMOS structure. It describes a series of experiments in which test patterns derived using different fault models are used to test 529 NMOS multiplexers. 12% of the chips tested and identified as being fault-free by a test set derived using the stuck-at fault model were faulty. In addition, two functional-level test sequences made up of identical test vectors arranged in different order were used to test the multiplexers. One correctly identified all the faulty circuits; the other identified 9% of the faulty circuits as being fault-free. The paper concludes that the stuck-at model is inadequate for testing MOS circuits, because of its use of a gate-level representation of the circuit under test. A more accurate method for generating and evaluating MOS circuit test patterns is to work from the switch-level representation of the circuit under test, testing for transistor stuck-on and stuck-open faults.<
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Physical faults in MOS circuits and their coverage by different fault models

VLSI circuits currently being designed are so complex that it is now extremely difficult to test them adequately to determine whether or not they have been processed correctly. Design for testability (DFT) techniques are often used in an attempt to ease this problem by identifying and redesigning potentially ‘difficult-to-test’ parts of the circuits. The ‘testability’ of the circuit is usually evaluated in terms of the stuck-at fault model. However, there have been growing doubts over the ability of this model to cover certain common faults that can occur in MOS processing (at present, the dominant VLSI technology). The paper describes software simulations of faults in simple NMOS logic circuits showing that not all fault effects in NMOS circuits are modellable as ‘stuck’ nodes. An improved fault model which would better reflect MOS fault effects has yet to be defined. Until such an improved model is available, DFT rules for MOS circuits are best regarded as provisional. We therefore conclude with a discussion of ad hoc ‘physical design for testability’ techniques that exploit current understanding of the relation between MOS faults and their fault effects.

S.J. Shaw

Papers

Physical faults in MOS circuits and their coverage by different fault models

Faults and fault effects in NMOS circuits - impact on design for testability