High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.

High aspect ratio silicon etch: A review

An intensive study has been performed to understand and tune deep reactive ion etch (DRIE) processes for optimum results with respect to the silicon etch rate, etch profile and mask etch selectivity (in order of priority) using state-of-the-art dual power source DRIE equipment. The
research compares pulsed-mode DRIE processes (e.g. Bosch technique) and mixed-mode DRIE processes (e.g. cryostat technique). In both techniques, an inhibitor is added to
fluorine-based plasma to achieve directional etching, which is formed out of an oxide-forming (O2) or a fluorocarbon (FC) gas (C4F8 or CHF3). The inhibitor can be introduced together with the etch gas, which is named a mixed-mode DRIE process, or the inhibitor can be added in a
time-multiplexed manner, which will be termed a pulsed-mode DRIE process. Next, the most convenient mode of operation found in this study is highlighted including some remarks to
ensure proper etching (i.e. step synchronization in pulsed-mode operation and heat control of the wafer). First of all, for the fabrication ......
 Enjoy reading . Henri Jansen 18 June 2008

https://iopscience.iop.org/article/10.1088/0960-1317/19/3/033001/pdf

Black silicon method X: a review on high speed and selective plasma etching of silicon with profile control: an in-depth comparison between Bosch and cryostat DRIE processes as a roadmap to next generation equipment

Microneedle technologies have the potential for expanding the capabilities of wearable health monitoring from physiology to biochemistry. This paper presents the fabrication of silicon hollow microneedles by a deep-reactive ion etching (DRIE) process, with the aim of exploring the feasibility of microneedle-based in-vivo monitoring of biomarkers in skin fluid. Such devices shall have the ability to allow the sensing elements to be integrated either within the needle borehole or on the backside of the device, relying on capillary filling of the borehole with dermal interstitial fluid (ISF) for transporting clinically relevant biomarkers to the sensor sites. The modified DRIE process was utilized for the anisotropic etching of circular holes with diameters as small as 30 μm to a depth of >300 μm by enhancing ion bombardment to efficiently remove the fluorocarbon passivation polymer. Afterward, isotropic wet and/or dry etching was utilized to sharpen the needle due to faster etching at the pillar top, achieving tip radii as small as 5 μm. Such sharp microneedles have been demonstrated to be sufficiently robust to penetrate porcine skin without needing any aids such as an impact-insertion applicator, with the needles remaining mechanically intact after repetitive penetrations. The capillary filling of DRIE-etched through-wafer holes with water has also been demonstrated, showing the feasibility of use to transport the analyte to the target sites. Microneedles are fabricated with a diameter as small as 30 µm and a tip radius of 5 µm, enabling skin penetration for in-vivo sampling of interstitial fluid. A key aspect to wearable health monitoring is the availability of devices that can sample key biomarkers in-vivo; microneedles are particularly promising for minimally invasive sampling of interstitial fluid. However, careful control of the microneedle size, geometry and quality are needed for effective penetration and sampling. Now, a team led by Bo Cui from University of Waterloo, and Eric Blondeel from ExVivo Labs Inc., demonstrates a modified deep reactive ion etching process for creating cone-shaped silicon microneedles with a hole opening for fluid extraction. Capillary filling of the holes is demonstrated, as well as repeatable penetration of porcine skin.

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Fabrication of sharp silicon hollow microneedles by deep-reactive ion etching towards minimally invasive diagnostics

The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization, etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is 'transferred' to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc) and chemistry (etch gases, flows, interactions with substrates, etc). In this paper, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers (BCPs) where nanopatterns are formed from the micro-phase separation of the system. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data are presented which shows that highly regular nanowire patterns of feature size below 20 nm can be created using etch optimization techniques and in this paper we demonstrate generation of crystalline silicon nanowire arrays with feature sizes below 8 nm. BCP techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity in these nanoscale resist patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing new etch processes.

https://iopscience.iop.org/article/10.1088/0022-3727/44/17/174012/pdf

Plasma etch technologies for the development of ultra-small feature size transistor devices

Atomically thin two-dimensional (2D) materials are promising candidates for sub-10 nm transistor channels due to their ultrathin body thickness, which results in strong electrostatic gate control. Properly scaling a transistor technology requires reducing both the channel length (distance from source to drain) and the contact length (distance that source and drain interface with semiconducting channel). Contact length scaling remains an unresolved epidemic for transistor scaling, affecting devices from all semiconductors, from silicon to 2D materials. Here, we show that clean edge contacts to 2D MoS2 provide immunity to the contact-scaling problem, with performance that is independent of contact length down to the 20 nm regime. Using a directional ion beam, in situ edge contacts of various metal-MoS2 interfaces are studied. Characterization of the intricate edge interface using cross-sectional electron microscopy reveals distinct morphological effects on the MoS2 depending on its thickness, from monolayer to few-layer films. Chromium is found to outperform other metals in the edge contact scheme, which is attributed to the shorter Cr-MoS2 bond length. Compared to scaled top contacts with 20 nm contact length, in situ edge contacts yield better performance with an effective contact length of ~ 1 nm and 18 times higher carrier injection efficiency. The in situ edge contacts also exhibit ~8 times higher performance compared to the best-reported edge contacts. Our work provides experimental evidence for a solution to contact scaling in transistors, using 2D materials with clean edge contact interfaces, opening a new way of designing devices with 2D materials.

Immunity to Scaling in MoS2 Transistors Using Edge Contacts.

Microelectromechanical system (MEMS) device fabrication often involves three dimensional structures with high aspect ratios. Moreover, MEMS designs require structures with different dimensions and aspect ratios to coexist on a single microchip. There is a well-documented aspect ratio dependent etching (ARDE) effect in deep silicon etching processes. For features with different dimensions etched simultaneously, the ARDE effect causes bigger features to be etched at faster rates. In practice, ARDE effect has many undesired complications to MEMS device fabrication. This article presents a physical model to describe the time division multiplex (TDM) plasma etch processes and thereafter the experimental results on ARDE lag reduction. The model breaks individual plasma etch cycles in the TDM plasma etch processes into polymer deposition, polymer removal, and spontaneous silicon etching stages. With the insights gained from the model and control over the passivation and etch steps, it has been demonstrated that ...

/pdf/aspect-ratio-dependent-etching-lag-reduction-in-deep-silicon-21y1arwrik.pdf

S. L. Lai

Papers

Aspect ratio dependent etching lag reduction in deep silicon etch processes