A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Sense-amp based adder with source follower evaluation tree

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique.

Performance of CMOS differential circuits

Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1.2 /spl mu/m MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates for moderate tree heights.

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Differential current switch logic: a low power DCVS logic family

Self-timed circuits with an appropriate handshake protocol can be used to eliminate the requirement for a global clock in a system. At the board level, asynchronous interfaces already make use of this approach. The natural extension of this concept is to use the same communication between blocks within an IC. To demonstrate this approach, self-timed circuits, or circuits which generate a completion signal, were used, along with interconnection circuits, following a four-cycle handshaking protocol, to design and fabricate a complete general-purpose digital signal processor (DSP). Internally, stages communicate at their own speed, which is an advantage because the speed of operation no longer is constrained by the slowest block in the system. The design methodology becomes modular, the blocks being decoupled with respect to their timing considerations. The DSP contains a full data path, with several feedback paths requiring synchronization between words at different stages of the pipe. Self-timed circuits are used throughout and all communication follows a handshaking protocol. >

A fully-asynchronous digital signal processor using self-timed circuits

An improved differential CMOS logic family called enabled/disabled CMOS differential logic (ECDL) is presented. An extension to this logic technique which enables the implementation of iterative network arrays is also presented. Two simple logic functions, a Gray-to-binary decoder and an XOR cell, are implemented to demonstrate this methodology. >

Implementation of iterative networks with CMOS differential logic

A single-phase clock has two edges. A clocking scheme utilizing the two edges of a single-phase clock to control the movement of data is presented. The scheme is similar to the two-phase nonoverlapping clocking scheme. A single-phase clock CMOS shift register to illustrate this clocking schemes is proposed. This shift register utilizes the bistable element, 'sense amplifier', to sense the state of its previous stage. There are two stages. The first stage triggers on the rising edge and the second stage triggers on the trailing edge. It is a static register with no minimum clocking frequency. Instead of four clock phases used in conventional CMOS dynamic shift registers, or two clock phases used in existing static registers, only one clock phase is used. This single-phase clocking scheme greatly reduces the overhead of having to route two or four clock signals around the chip. It also eliminated the clock skewing difficulty plaguing the conventional shift register. >

S.-L. Lu

Papers

Implementation of iterative networks with CMOS differential logic

A safe single-phase clocking scheme for CMOS circuits