In this paper, an easily testable machine is defined as one which possesses: 1) a distinguishing sequence of length [log2 n] which forces the machine into a specific state S1, and 2) transfer sequences of length at most [1og2 n] to carry the machine from state S1 to state Si for all i. A design procedure is presented in which an arbitrary machine is augmented to an easily testable machine by adding two special input symbols to the original machine. An efficient procedure is also described for designing checking experiments for the easily testable machines. For an n-state, m-input symbol machine, this procedure gives a bound on the length of the checking experiment that is approximately mn[log2,n]. Furthermore, the total checking experiments are preset.

Easily Testable Sequential Machines with Extra Inputs

This paper surveys and summarizes the major contributions to the theory and practice of testable logic design. The first part, dealing with the theoretical procedures, discusses the design of easily testable combinational, sequential, and iterative networks, illustrating major techniques with common running examples. The second part comments on the more practical aspects such as board layout, test point siting, and other facilities for easing the problems associated with testing.

Recent Developments in the Theory and Practice of Testable Logic Design

By augmenting a given sequential machine M with two extra input symbols Ie1 and Ie2 and with one extra output terminal Z', a method is developed in this paper for designing an efficient checking experiment for the machine M and for its fault diagnosis to cover the types of faults which may result in an increase in the number of states of the original machine M. The method is an extension of the works of Fujiwara et al.[6], and the scheme of modification never alters the modified machine M' from its easily testable nature as defined by Fujiwara et al [16]. The checking sequences exhibit remarkable savings of the number of input symbols for many sequential machines having a large number of states as compared to that of Fujiwara et al [16].

On a Novel Approach of Fault Detection in an Easily Testable Sequential Machine with Extra Inputs and Extra Outputs

This paper is concerned with the problem of designing easily testable sequential machines, output-observable machines, for which there exist very short checking experiments. A sequential machine for which any initial state can be uniquely determined only by the output response is said to be output-observable. An algorithm is developed to modify a given machine to an output-observable one by adding a minimum number of extra outputs. This method is based on the fact that the output-observable realization of a given machine M exists if and only if M is semi-FSR realizable (a special type of feedback shift register realization).

Design of Diagnosable Sequential Machines Utilizing Extra Outputs

The bound on the length of checking experiments derived by Murakami et al. [1] is improved by using a more efficient output specification in the counter cycle.

An Improved Bound on the Length of Checking Experiments for Sequential Machines with Counter Cycles

By a checking sequence for a sequential machine, we mean an input-output sequence with a special property such that, when the input sequence is applied to the machine, the decision whether or not the machine operates correctly can be made by comparing the output sequence with the output of the machine.

S. Murakami

Papers

Sequential Machines Capable of Fault Diagnosis