Showing papers in "IEEE Transactions on Computers in 1970"
TL;DR: A method is developed herein to use the Karhunen-Loeve expansion to extract features relevant to classification of a sample taken from one of two pattern classes.
Abstract: The Karhunen-Lo6ve expansion has been used previously to extract important features for representing samples taken from a given distribution. A method is developed herein to use the Karhunen-Loeve expansion to extract features relevant to classification of a sample taken from one of two pattern classes. Numerical examples are presented to illustrate the technique.
562 citations
TL;DR: The logic-in-memory computer points to a new direction for achieving orders of magnitude increase in computer performance, since the computer is specifically organized for large-scale integration, the increased performance might be obtained for a comparatively small dollar cost.
Abstract: If, as presently projected, the cost of microelectronic arrays in the future will tend to reflect the number of pins on the array rather than the number of gates, the logic-in-memory array is an extremely attractive computer component. Such an array is essentially a microelectronic memory with some combinational logic associated with each storage element. A logic-in-memory computer is described that is organized around a logic-enhanced ``cache'' memory array. Used as a cache, a logic-in-memory array performs as a high-speed buffer between a conventional CPU and a conventional memory. The effect on the computer system of the cache and its control mechanism is to make the main memory appear to have all of the processing capabilities and almost the same performance as the cache. Operations within the array are naturally organized as operations on blocks of data called ``sectors.'' Among the operations that can be performed are arithmetic and logical operations on pairs of elements from two sectors, and a variety of associative search operations on a single sector. For such operations, the main memory of the computer appears to the program to be composed of a collection of logic-in-memory arrays, each the size of a sector. Because of the high-speed, highly parallel sector operations, the logic-in-memory computer points to a new direction for achieving orders of magnitude increase in computer performance. Moreover, since the computer is specifically organized for large-scale integration, the increased performance might be obtained for a comparatively small dollar cost.
265 citations
TL;DR: In this paper, a methodical procedure for organization of fault detection experiments for synchronous sequential machines possessing distinguishing sequences (DS) is given, based on the transition checking approach, which is considered in three concatenative parts: 1) the initial sequence which brings the machine under test into a specific state, 2) the α-sequence to recognize all the states and to establish the information about the next states under the input DS, and 3) the β -sequence to check all the individual transitions in the state table.
Abstract: A methodical procedure for organization of fault detection experiments for synchronous sequential machines possessing distinguishing sequences (DS) is given. The organization is based on the transition checking approach. The checking experiment is considered in three concatenative parts: 1) the initial sequence which brings the machine under test into a specific state, 2) the α-sequence to recognize all the states and to establish the information about the next states under the input DS, and 3) the β-sequence to check all the individual transitions in the state table.
248 citations
TL;DR: For a single instruction stream–single data stream organization the problem of simultaneously issuing several instructions is studied.
Abstract: For a single instruction stream–single data stream organization the problem of simultaneously issuing several instructions is studied.
238 citations
TL;DR: A homomorphism of the de Bruijn graph that maps a graph of order n onto one ofOrder n-1 and its applications to the design of nonsingular feedback shift registers are discussed and a recursive formula for a feedback function that generates a cycle of maximum length is obtained.
Abstract: A homomorphism of the de Bruijn graph that maps a graph of order n onto one of order n-1 and its applications to the design of nonsingular feedback shift registers are discussed. The properties preserved under this mapping suggest a new design technique whose main advantage is due to the fact that the problem of designing a desired n-stage shift register may be reduced to a problem of order n-1 or less. Among the results obtained is a recursive formula for a feedback function that generates a cycle of maximum length.
156 citations
TL;DR: It is proved that the algorithm will find all the prime implicants of a Boolean function, and the algorithm is implemented by a computer program in the LISP language.
Abstract: This paper describes an algorithm which will generate all the prime implicants of a Boolean function. The algorithm is different from those previously given in the literature, and in many cases it is more efficient. It is proved that the algorithm will find all the prime implicants. The algorithm may possibly generate some nonprime implicants. However, using frequency orderings on literals, the experiments with the algorithm show that it usually generates very few ( possibly none) nonprime implicants. Furthermore, the algorithm may be used to find the minimal sums of a Boolean function. The algorithm is implemented by a computer program in the LISP language.
156 citations
TL;DR: In order to avoid the time delays associated with linearly convergent division based on subtraction, other iterative schemes can be used based on series expansion of the reciprocal, multiplicative sequence, or additive sequence convergent to the quotient.
Abstract: In order to avoid the time delays associated with linearly convergent division based on subtraction, other iterative schemes can be used. These are based on 1) series expansion of the reciprocal, 2) multiplicative sequence, or 3) additive sequence convergent to the quotient. These latter techniques are based on finding the root of an arbitrary function at either the quotient or reciprocal value. A Newton-Raphson iteration or root finding iteration can be used.
153 citations
[...]
TL;DR: A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described, which multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns.
Abstract: A number of schemes for implementing a fast multiplier are presented and compared on the basis of speed, complexity, and cost. A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described. This multiplier multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns. The cost of the integrated circuits was less than $ 500.
139 citations
TL;DR: Applications to digital filtering computations are considered which illustrate that log-antilog multiplication is not simpler than an array multiplier for computing single products, but is useful for parallel digital filter banks and multiplicative digital filters.
Abstract: An approximate method for rapid multiplication or division with relatively simple digital circuitry is described. The algorithm consists of computing approximate binary logarithms, adding or subtracting the logarithms, and computing the approximate anti- logarithm of the resultant. Using a criteria of minimum mean square error, coefficients for the approximations are developed. An error analysis is given for three cases in which the algorithm is useful. Finally, applications to digital filtering computations are considered which illustrate that log-antilog multiplication is not simpler than an array multiplier for computing single products, but is useful for parallel digital filter banks and multiplicative digital filters.
137 citations
TL;DR: A novel structure for a hardwired fast Fourier transform (FFT) signal processor that promises to permit digital spectrum analysis to achieve throughput rates consistent with extremely wide-band radars is described.
Abstract: This paper describes a novel structure for a hardwired fast Fourier transform (FFT) signal processor that promises to permit digital spectrum analysis to achieve throughput rates consistent with extremely wide-band radars. The technique is based on the use of serial storage for data and intermediate results and multiple arithmetic units each of which carries out a sparse Fourier transform. Details of the system are described for data sample sizes that are binary multiples, but the technique is applicable to any composite number.
127 citations
TL;DR: A piecewise linear method is described which is being used in the on-line pattern analysis and recognition system (OLPARS) and it is shown that it can be used to discriminate between vector samples from two classes.
Abstract: In solving pattern classification problems, many researchers have successfully used the Fisher linear discriminant as the optimal linear method for discriminating between vector samples from two classes. With the introduction of on-line, interactive, graphic systems, it has become conveniently possible to extend the discrimination logic to piecewise linear methods. This paper describes such a method which is being used in the on-line pattern analysis and recognition system (OLPARS).
TL;DR: It is shown how the Kronecker product can be mathematically defined and efficiently implemented using a matrix factorization method and a generalized spectral analysis is suggested, and a variety of examples are presented displaying various properties of the decompositions possible.
Abstract: A technique is presented to implement a class of orthogonal transformations on the order of pN log p N operations. The technique is due to Good [1] and implements a fast Fourier transform, fast Hadamard transform, and a variety of other orthogonal decompositions. It is shown how the Kronecker product can be mathematically defined and efficiently implemented using a matrix factorization method. A generalized spectral analysis is suggested, and a variety of examples are presented displaying various properties of the decompositions possible. Finally, an eigenvalue presentation is provided as a possible means of characterizing some of the transforms with similar parameters.
TL;DR: It is proven that if certain assumptions are satisfied, then the algorithm will derive the optimal partition in the sense of maximum separation.
Abstract: An algorithm is presented which partitions a given sample from a multimodal fuzzy set into unimodal fuzzy sets. It is proven that if certain assumptions are satisfied, then the algorithm will derive the optimal partition in the sense of maximum separation.
TL;DR: The number of threshold functions of eight variables is counted by ILLIAC II, the computer of the University of Illinois and sets of optimum weights of majority elements realizing these functions also are investigated.
Abstract: The number of threshold functions of eight variables is counted by ILLIAC II, the computer of the University of Illinois. Sets of optimum weights of majority elements realizing these functions also are investigated. Actually, canonical positive self-dual threshold functions of nine variables are investigated instead of directly investigating threshold functions of eight variables because it is easier to deal with them. The number and optimum weights of threshold functions of eight variables are easily obtained from these functions of nine variables and their realization.
TL;DR: The method presented here for solving the "hidden-line problem" for computer-drawn polyhedra is believed to be faster than previously known methods.
Abstract: The "hidden-line problem" for computer-drawn polyhedra is the problem of determining which edges, or parts of edges, of a polyhedra are visible from a given vantage point. This is an important problem in computer graphics, and its fast solution is especially critical for on-line CRT display applications. The method presented here for solving this problem is believed to be faster than previously known methods. An edge classification scheme is described that eliminates at once most of the totally invisible edges. The remaining, potentially visible edges are then tested in paths, which eventually cover the whole polyhedra. These paths are synthesized in such a way as to minimize the number of calculations. Both the case of a cluster of polyhedra and the illumination problem in which a polyhedron is illuminated from a point source of light are treated as applications of the general algorithm. Several illustrative examples are included.
TL;DR: The nonparametric representation of the curve, which is widely used since it lends itself to realization by ordinary DDA technique, is shown to be fully competitive.
Abstract: The process of converting a mathematically defined curve into unit steps along a fixed axis in digital technique is known as interpolation. The representation of the curve may be parametric or nonparametric. The parametric representation is widely used since it lends itself to realization by ordinary DDA technique. However, the nonparametric representation is shown to be fully competitive. In many cases, e.g., circle generation, it seems to be advantageous because it eliminates the risk of curve degradation.
TL;DR: The aim of this paper is to obtain a procedure for finding a minimum state nondeterministic finite automaton (NDA) equivalent to a given (in general, nondetergetic) finite Automaton.
Abstract: The aim of this paper is to obtain a procedure for finding a minimum state nondeterministic finite automaton (NDA) equivalent to a given (in general, nondeterministic) finite automaton. Given a finite automaton A, we derive from A a matrix of 1' s and 0's, called a reduced automaton matrix RAM) of A, in a certain way and show that each state of A corresponds to a grid over the RAM. A grid consists of a set of rows and a set of columns of an RAM such that only 1's appear at the intersections. It is also shown that the union of all the grids, each of which corresponds to a state of A, covers all the 1 entries of an RAM.
IBM1
TL;DR: A new type of universal logic modules (ULM's) called the Q-type is presented, which are superior to the existing ULM's in the sense that they require fewer input/output terminals when n≥6 where n is the number of input variables of the ULM.
Abstract: Recent advances in integrated circuit technology and its potential advantage in logical design have motivated the search for modular synthesis techniques for logic networks. This problem may be divided into two parts: find appropriate modules; and develop efficient synthesis techniques for logic networks using a minimum number of modules. In this paper a new type of universal logic modules (ULM's) called the Q-type is presented. The Q-type ULM's are superior to the existing ULM's in the sense that they require fewer input/output terminals when n≥6 where n is the number of input variables of the ULM. Various techniques for synthesizing a logic network with a small number of ULM's are discussed. A much simpler type of modules, which is suitable to realize any symmetric or partially symmetric function and can be used as auxiliary building blocks for realizing any given logic function, is presented. A special kind of ULM's, called serially controlled ULM's which has only n+ 3 input/ output terminals, is also presented. For a ULM of this kind the signals for specifying the logic function to be realized are serially applied to one of its input terminals.
TL;DR: This paper is an attempt to develop minimization algorithms for switching circuits based on Reed-Muller canonic forms for obtaining minimal modulo 2 or complement modulo2 sum-of- products expressions of any arbitrary single-output or multiple-output switching function with fixed polarities of the input variables.
Abstract: This paper is an attempt to develop minimization algorithms for switching circuits based on Reed-Muller canonic forms. In particular, algorithms are presented for obtaining minimal modulo 2 or complement modulo 2 sum-of- products (or sums) expressions of any arbitrary single-output or multiple-output switching function with fixed polarities of the input variables.
TL;DR: An on-line interactive graphics system which has been designed to solve the problems of pattern analysis and pattern classification and a discussion of an application of the system to the handprinted character recognition problem is included.
Abstract: This paper describes an on-line interactive graphics system which has been designed to solve the problems of pattern analysis and pattern classification. A wide variety of both classical and unique mathematical algorithms, along with their graphic system implementation, are discussed. A discussion of an application of the system to the handprinted character recognition problem is included.
TL;DR: This work states two basic requirements that criteria for grouping data without supervision should meet and discusses several criteria in terms of these requirements and introduces a linear transformation of the data.
Abstract: Many algorithms for grouping data without supervision depend on some criterion. We state two basic requirements such criteria should meet and we discuss several criteria in terms of these requirements. An attempt to satisfy both requirements simultaneously with a simple criterion leads us to introduce a linear transformation of the data. Although our principal result is for a two category problem, we present discussion and an example for the many category problem as well.
TL;DR: The main drawbacks, as pointed out by a number of authors, are the difficulties associated with the implementation of the functional basic set and the lack of adequate simplify techniques.
Abstract: Many-valued switching systems have been of considerable academic interest, despite the apparent inability to use them in practical applications. The main drawbacks, as pointed out by a number of authors, are the difficulties associated with the implementation of the functional basic set and the lack of adequate simplification techniques.
TL;DR: An algorithm for minimizing the bit dimension of READ- ONLY memories employed in the control section of microprogrammed digital computers is illustrated.
Abstract: An algorithm for minimizing the bit dimension of READ- ONLY memories employed in the control section of microprogrammed digital computers is illustrated. The algorithm employs techniques which are well known in switching theory, such as compatibility classes and covering tables of the prime implicant type.
TL;DR: A procedure for factoring of the N×N matrix representing the discrete Fourier transform is presented which does not produce shuffled data, and is shown to be most efficient for Na power of two.
Abstract: A procedure for factoring of the N×N matrix representing the discrete Fourier transform is presented which does not produce shuffled data. Exactly one factor is produced for each factor of N, resulting in a fast Fourier transform valid for any N. The factoring algorithm enables the fast Fourier transform to be implemented in general with four nested loops, and with three loops if N is a power of two. No special logical organization, such as binary indexing, is required to unshuffle data. Included are two sample programs, one which writes the equations of the matrix factors employing the four key loops, and one which implements the algorithm in a fast Fourier transform for N a power of two. The algorithm is shown to be most efficient for Na power of two.
TL;DR: The procedure to design an optimal buffer system in the sense of minimal cost (tradeoff between buffer cost and transmission cost) is discussed and the relationships among overflow probabilities, buffer size, and expected queuing delay due to buffering are obtained.
Abstract: A queuing model with a limited waiting room (buffer), Poisson arrivals, multiple synchronous servers (synchronous transmission channels), and constant services is studied. Using traffic intensity and number of transmission lines as parameters, the relationships among overflow probabilities, buffer size, and expected queuing delay due to buffering are obtained. These relationships are represented in graphs which are provided as a guide to the design of buffer systems. An example is given to illustrate the use of these results in buffer design problems. In addition, the procedure to design an optimal buffer system in the sense of minimal cost (tradeoff between buffer cost and transmission cost) is discussed.
TL;DR: Dynamic microprogramnming (i. e., utilizing a READ/ WRITE microstorage) allows the structure of a computer to be altered to suit a problem at hand and results in major efficiencies in running time for nonarithmetic programs (e. g., compilers).
Abstract: Dynamic microprogramnming (i. e., utilizing a READ/ WRITE microstorage) allows the structure of a computer to be altered to suit a problem at hand and results in major efficiencies (an order of magnitude) in running time for nonarithmetic programs (e. g., compilers).
TL;DR: An upper bound is derived for the time required to add numbers modulo 2n, using circuit elements with a limited fan-in and unit delay, and assuming that all numbers have the usual binary encoding.
Abstract: An upper bound is derived for the time required to add numbers modulo 2n, using circuit elements with a limited fan-in and unit delay, and assuming that all numbers have the usual binary encoding. The upper bound is within a factor (1 + e) of Winograd's lower bound (which holds for all encodings), where e→0 as n→∞, and only O(n log n) circuit elements are required.
TL;DR: A common recursive formulation is presented for determining: all the prime implicants, and an irredundant normal form of any completely or incompletely specified Boolean function given in canonical form.
Abstract: A common recursive formulation is presented for determining: 1) all the prime implicants, and 2) an irredundant normal form of any completely or incompletely specified Boolean function given in canonical form. Formulas for specific operators Pi and lrr2 solving these problems are given and recursive partitioned list algorithms are described for them. The solution of both of the above problems through recursive partitioned list algorithms is significantly faster than through the corresponding nonrecursive algorithms.
TL;DR: A cellular-logic approach is used to generate a family of multiple-output combinational switching circuits containing closed loops and composed of simple gates, which contain fewer gates than any loop-free realizations.
Abstract: A cellular-logic approach is used to generate a family of multiple-output combinational switching circuits containing closed loops ( of the type that normally generate sequential behavior) and composed of simple gates. These networks contain fewer gates than any loop-free realizations. Some members of the family are oscillatory, while others are stable with multiple stable states, but the outputs remain quiescent in both cases. This result appears to have repercussions on some of the well-known optimality results of switching theory.
TL;DR: A scheme for detecting errors in ADD, COMPLEMENT, SHIFT, and ROTATE operations using a residue check circuitry derived by a suitable application of a code called biresidue arithmetic code described here.
Abstract: In an earlier paper [11] a scheme for detecting errors in ADD, COMPLEMENT, SHIFT, and ROTATE operations using a residue check circuitry was presented. A scheme for error location and correction in those operations is derived by a suitable application of a code called biresidue arithmetic code described here. Any single error position can be located and also corrected by use of two residue checkers which work separately and in parallel with the arithmetic unit. The estimated cost of redundancy is approximately the same as that required for duplication of the arithmetic unit.