S
S Nithyashree
Researcher at R.V. College of Engineering
Publications - 1
S Nithyashree is an academic researcher from R.V. College of Engineering. The author has contributed to research in topics: Verilog. The author has co-authored 1 publications.
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Proceedings ArticleDOI
Design of an efficient vedic binary squaring circuit
S Nithyashree,Y Chandu +1 more
TL;DR: A comparative study of the projected architecture and the prevailing multipliers, on the premise of delay and space utilization is presented and the simulation outcome proves that the design projected employing Nikhilam sutra improves the performance significantly.