The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.

Miller and noise effects in a synchronizing flip-flop

Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules. >

Metastability behavior of CMOS ASIC flip-flops in theory and test

Optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops are obtained by using the AC small-signal analysis in the frequency domain instead of the usual time-domain approach. The Miller effect on the metastability is investigated for the configurations which have a better metastable resolving capability. The mean time between failure (MTBF) was measured, and the result verifies this new design approach. The power supply disturbance and temperature variation effects on the metastability were also measured, and the data show that a 0.75-V change of power supply voltage and 75 degrees C change of chip temperature cause a four orders of magnitude difference in the MTBF. The simulation results using the AC small-signal frequency-domain analysis agree well with the measurement data for the different power supply voltages and chip temperatures, confirming that an AC small-signal approach can be used more widely for the design of metastable hardened latch/flip-flops. The other parameters are discussed in terms of their effects on the latch/flip-flop's susceptibility to the metastable state. >

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Metastability of CMOS latch/flip-flop

This paper characterizes the effects of loading, power supply, and technology scaling on the metastable parameters of CMOS latches used as synchronizers. Results from 2 /spl mu/ and 1.2 /spl mu/ test chips designed to measure the performance of buffered and unbuffered CMOS latches with respect to loading and supply voltages are presented. While the optimum synchronizer in CMOS technology has been previously shown to be an unbuffered, unloaded latch, our results show that buffered latches have better mean time between failure (MTBF) performance for all loads greater than a fanout of one with sufficient resolution time. However, MTBF performance still degrades exponentially with loading in buffered latches. A normalization scheme to compare latches with different supplies and technologies is presented with data from the test chips. Improvements in latch metastable parameters with increased supply or reduced channel length are shown to be reduced when the effects of shorter on-chip delays are factored in. In a given technology, normalized metastable parameters are shown to be unchanged for a wide range of supply voltages, allowing calculation of metastable parameters in supply voltages not explicitly measured. >

Metastability in CMOS library elements in reduced supply and technology scaled applications

In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper delay or phase control, a metastability problem occurs. Self-tested self-synchronization (STSS) was proposed to solve this problem. In this paper, we describe two STSS methods, STSS-1 and STSS-2, implemented by two-phase input ports for parallel/serial data transfer. Measurements on a test chip for the two methods show that a data rate of 750 Mb/s is reached with 3.6-V power supply in 0.6-/spl mu/m CMOS. Comparison is made between STSS-1 and STSS-3.

Self-tested self-synchronization circuit for mesochronous clocking

The synchronization performance of CMOS circuits is examined theoretically and experimentally. Criteria for maximizing CMOS gain are determined and are then compared with NMOS gain curves. The phase characteristics of metastability are identified. Experimental measurements of error rate are made on a CMOS test circuit, and the gain-bandwidth product for the circuit is determined from these data.

S.T. Flannagan

Papers

Synchronization reliability in CMOS technology